MIC2155_0911 Datasheet, PDF (13/35 Pages) Micrel Semiconductor – Two-Phase, Single-Output, PWM Synchronous Buck Control IC

Micrel, Inc.
VEN1/2
Slope = I_SS/C_SS
VSS
V_OUT
Figure 3. Soft Start Waveforms
Figure 4. Soft Start Circuit
The output voltage starts to rise when V_SS is
approximately 1 diode drop above ground, 0.6V.
The startup delay and output voltage risetime can be
approximated using the formula shown below:
Delay
t_d
=
C_SS × 0.6V
I_SS
Risetime
t_R
=
C_SS × V_OUT
14 × I_SS
The soft start pin is discharged under the following
conditions:
• EN1 pin de-asserted
• UVLO on the VIN1 or VDD pins
• Overcurrent
• Overvoltage (latched off)
MIC2155/2156
Enable
There is an enable pin for each of the two channels.
Asserting EN1 will enable Channel 1 gate drive and
release the soft start circuit. De-asserting EN1 will
disable the gate drive, discharge C_SS and disable V_DD. It
will bring the controller into a low current off state.
Enable 2 only controls switching of Channel 2. Disabling
Channel 2 stops the switching of the power FETs on
Channel 2 which reduces the V_DD current draw. This can
improve efficiency when operating at low output current,
especially when large MOSFETs are used.
Supply Voltages and Internal References
The MIC2155/6 is powered from a 4.5V to 14.5V supply.
The two input supply pins (VIN1 and VIN2) are
connected together in most applications. They are
powered separately in configurations with two input
supply voltages.
VIN1 supplies an internal LDO, which generates the
VDD supply voltage. V_DD is used to power the gate drive
circuitry and must be externally decoupled to the power
ground pins (PGND1 and PGND2). A 10µF Ceramic
capacitor is recommended for most applications. The
AVDD pin is the supply pin for the Bandgap reference
and internal analog circuits. A small RC filter
(10Ω/0.1µF) connected to AVDD is recommended to
help attenuate switching noise from the VDD supply.
The dropout of the internal VDD regulator causes VDD
to drop if VIN1 is below 6V. When operating below 6V,
VDD may be jumpered to VIN1. This bypasses the
internal LDO and prevents VDD from dropping out.
An LDO or simple series pass regulator can be used to
limit the VDD voltage for applications with an input
voltage that spans above and below the 6V maximum
V_DD limit. Figures 5 and 6 illustrate two examples of
regulating VDD with external circuitry.
C_IN
1µF
C _VDD
10µF
C_BST
Figure 5. LDO Regulator
November 2009
13
M9999-111209-B