MIC2582_09 Datasheet, PDF (14/25 Pages) Micrel Semiconductor – Single Channel Hot Swap Controllers

Micrel, Inc.
following equation:
Output Voltage Slew Rate, dV_OUT/dt = ^ILIM
(4)
C_LOAD
where I_LIM is the programmed current limit value.
Consequently, the value of C_FILTER must be selected to
ensure that the overcurrent response time, t_OCSLOW,
exceeds the time needed for the output to reach its final
value. For example, given a MOSFET with an input
capacitance C_ISS = C_GATE = 4700pF, C_LOAD is 2200µF,
and I_LIM is set to 6A with a 12V input, then the load
capacitance dominates as determined by the calculated
INRUSH > I_LIM. Therefore, the output voltage slew rate
determined from Equation 4 is:
Output Voltage Slew Rate, dV_OUT/dt = ^6A _{= 2.73} ^V
2200μF
ms
and the resulting t_OCSLOW needed to achieve a 12V
output is approximately 4.5ms. (See Power-On Reset
and Overcurrent Timer Delays section to calculate
t_OCSLOW).
GATE Capacitance Dominated Start-Up
In this case, the value of the load capacitance relative to
the GATE capacitance is small enough such that the
load current during start-up never exceeds the current
limit threshold as determined by Equation 3. The
minimum value of C_GATE that will ensure that the current
limit is never exceeded is given by the equation below:
C_GATE (min) =
I_GATE
I _LIM
×
C_LOAD
(5)
where C_GATE is the summation of the MOSFET input
capacitance (C_ISS) and the value of the external
capacitor connected to the GATE pin of the MIC2582/83
to ground. Once C_GATE is determined, use the following
equation to determine the output slew rate for gate
capacitance dominated start-up.
dV_OUT/dt
=
I _GATE
C_GATE
(6)
Table 1 depicts the output slew rate for various values of
C_GATE.
I_GATE = 17µA
C_GATE
dV_OUT/dt
0.001µF
17V/ms
0.01µF
1.7V/ms
0.1µF
0.17V/ms
1µF
0.017V/ms
Table 1. Output Slew Rate Selection for GATE
Capacitance Dominated Start-Up
MIC2582/MIC2583
Current Limiting and Dual-Level Circuit Breaker
Many applications will require that the inrush and steady
state supply current be limited at a specific value in order
to protect critical components within the system.
Connecting a sense resistor between the VCC and
SENSE pins sets the nominal current limit value of the
MIC2582/83 and the current limit is calculated using
Equation 2.
The MIC2582/83 also features a dual-level circuit
breaker triggered via 50mV and 100mV current-limit
thresholds sensed across the VCC and SENSE pins.
The first level of the circuit breaker functions as follows.
For the MIC2583/83R, once the voltage sensed across
these two pins exceeds 50mV, the overcurrent timer, its
duration set by capacitor C_FILTER, starts to ramp the
voltage at C_FILTER using a 6.5µA constant current source.
If the voltage at C_FILTER reaches the overcurrent timer
threshold (V_TH) of 1.24V, then C_FILTER immediately
returns to ground as the circuit breaker trips and the
GATE output is immediately shut down. The default
overcurrent time period for the MIC2582/83 is 5µs. For
the second level, if the voltage sensed across VCC and
SENSE exceeds 100mV at any time, the circuit breaker
trips and the GATE shuts down immediately, bypassing
the overcurrent time period. The MIC2582-MYM option
is equipped with only a single circuit breaker threshold
(50mV). To disable current limit and circuit breaker
operation, tie the SENSE and VCC pins together and the
C_FILTER (MIC2583/83R) pin to ground.
Output Undervoltage Detection
The MIC2582/83 employ output undervoltage detection
by monitoring the output voltage through a resistive
divider connected at the FB pin. During turn on, while the
voltage at the FB pin is below the threshold (V_FB), the
/POR pin is asserted low.
Once the FB pin voltage crosses V_FB, a 2.5µA current
source charges capacitor C_POR. Once the CPOR pin
voltage reaches 1.24V, the time period t_POR elapses as
the CPOR pin is pulled to ground and the /POR pin goes
HIGH. If the voltage at FB drops below V_FB for more than
10µs, the /POR pin resets for at least one timing cycle
defined by t_POR (See Applications Information for an
example).
Power-On Reset and Overcurrent Timer Delays
The Power-On Reset delay, t_POR, is the time period for
the /POR pin to go HIGH once the voltage at the FB pin
exceeds the power-good threshold (V_FB). A capacitor
connected to CPOR sets the interval and is determined
by using Equation 1 with V_TH substituted for V_START. The
resulting equation becomes:
( ) t_POR
=
C_POR
×
V_TH
I_CPOR
≅ 0.5 × C_POR
μF
(7)
where the Power-On Reset threshold (V_TH) and timer
April 2009
14
M9999-043009-C