MIC2166_1009 Datasheet, PDF(13/28 Page) Micrel Semiconductor – Adaptive On-Time DC-DC Controller Hyper Speed Control™ Family

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MIC2166_1009 Datasheet, PDF (13/28 Pages) Micrel Semiconductor – Adaptive On-Time DC-DC Controller Hyper Speed Control™ Family

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Micrel, Inc.

Using the typical VCL value of 133mV, the current limit

value is roughly estimated as:

ICL

133mV

RDS(ON)

For designs where the current ripple is significant

compared to the load current IOUT, or for low duty-cycle

operation, calculating the current limit ICL should take

into account that one is sensing the peak inductor

current and that there is a blanking delay of

approximately 150ns.

ICL

133mV

RDS(ON)

VOUT Ã tDLY

ÎIL(PP)

(2)

ÎIL(PP)

VOUT Ã (1 â D)

f SW ÃL

(3)

where:

VOUT = Output voltage

tDLY = Current-limit blanking time, 150ns typical

ÎIL(PP) = Inductor current ripple peak-to-peak value

D = Duty Cycle

fSW = Switching frequency

The MOSFET RDS(ON) varies between 30% to 40% with

temperature; therefore, it is recommended to add 50%

margin to ICL in the above equation to avoid false current

limiting due to increased MOSFET junction temperature

MIC2166

rise. It is also recommended to connect SW pin directly

to the drain of the low-side MOSFET to accurately sense

the MOSFETs RDS(ON).

MOSFET Gate Drive

The MIC2166 high-side drive circuit is designed to

switch an N-Channel MOSFET. The typical application

schematic shows a bootstrap circuit, consisting of D1 (a

Schottky diode is recommended) and CBST. This circuit

supplies energy to the high-side drive circuit. Capacitor

CBST is charged while the low-side MOSFET is on and

the voltage on the SW pin is approximately 0V. When

the high-side MOSFET driver is turned on, energy from

CBST is used to turn the MOSFET on. As the high-side

MOSFET turns on, the voltage on the SW pin increases

to approximately VIN. Diode D1 is reversed biased and

CBST floats high while continuing to keep the high-side

MOSFET on. The bias current of the high-side driver is

less than 10mA so a 0.1Î¼F to 1Î¼F is sufficient to hold

the gate voltage with minimal droop for the power stroke

(high-side switching) cycle, i.e., ÎBST = 10mA x

1.67Î¼s/0.1Î¼F = 167mV. When the low-side MOSFET is

turned back on, CBST is recharged through D1. A small

resistor RG at BST pin can be used to slow down the

turn-on time of the high-side N-channel MOSFET.

The drive voltage is derived from the internal linear

regulator VDD. The nominal low-side gate drive voltage is

VDD and the nominal high-side gate drive voltage is

approximately VDD â VDIODE, where VDIODE is the voltage

drop across D1. A dead-time of approximate 30ns delay

between the high-side and low-side driver transitions is

used to prevent current from simultaneously flowing

unimpeded through both MOSFETs.

September 2010

M9999-092410-C

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