MIC74_14 Datasheet, PDF (12/20 Pages) Micrel Semiconductor – 2-Wire Serial I/O Expander and Fan Controller

Micrel, Inc.
Application Information
Bit Transfer
The data received on the DATA pin must be stable during
the high period of the clock.
MIC74
Figure 3. Acceptable Bit Transfer Conditions
Data can change state only when the CLK line is low.
Refer to the figure above.
Start and Stop Conditions
Two unique bus situations define start and stop
conditions. A high-to-low transition of the DATA line while
CLK is high indicates a start condition. A low-to-high
transition of the DATA line while CLK is high defines a
stop condition. See Figure 4.
Figure 4. Start and Stop Definitions
Start (leading edge of start) and stop (trailing edge of
stop) conditions are always generated by the bus master
(host). After a start condition, the bus is considered to be
busy. The bus becomes free again after a certain time
following a stop condition or after both CLK and DATA
lines remain high for more than 50µs.
Serial Byte Format
Every byte consists of 8 bits. Each byte transferred on
the bus must be followed by an acknowledge bit. Bytes
are transferred with the MSB (most significant bit) first.
See Figure 5.
Figure 5. Serial Byte Format
Acknowledge and Not Acknowledge
The acknowledge related clock pulse is generated by the
master. The transmitter releases the DATA line (high)
during the acknowledge clock cycle.
In order to acknowledge (ACK) a byte, the receiver must
pull the DATA line low during the high period of the clock
pulse according the bus timing specifications. A slave
device that wishes to not acknowledge a byte must let the
DATA line remain high during the acknowledge clock
pulse. See Figure 6.
Figure 6. Acknowledge and Not Acknowledge
September 30, 2014
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Revision 3.0