MIC74_14 Datasheet, PDF (10/20 Pages) Micrel Semiconductor – 2-Wire Serial I/O Expander and Fan Controller

Micrel, Inc.
MIC74
Table 9. Register Summary
Register
Name
Register
Description
DEV_CFG
DIR
OUT_CFG
STATUS
INT_MASK
DATA
FAN_SPEED
Device configuration
I/O direction
Output configuration
Interrupt status
Interrupt mask
General purpose I/O
Fan speed
Address
Binary
Hex
0000 0000b
00h
0000 0001b
01h
0000 0010b
02h
0000 0011b
03h
0000 0100b
04h
0000 0101b
05h
0000 0110b
06h
Available
Options
8-bit read/write
8-bit read/write
8-bit read/write
8-bit read
8-bit read/write
8-bit read/write
8-bit read/write
Power-On Default
Binary
Hex
0000 0000b
00h
0000 0000b
00h
0000 0000b
00h
0000 0000b
00h
0000 0000b
00h
1111 1111b
FFh
0000 0000b
00h
Fan Start-Up
Any time the fan speed register contains zero (fan is off)
and then a nonzero value is written to FAN_SPEED, the
/FS[2:0] and /SHDN outputs will assume the highest fan
speed state for approximately one second (t_START).
Following this interval, the state of the fan speed control
outputs will assume the value indicated by the contents of
FAN_SPEED. This insures that the fan will start reliably
when low speed operation is desired. The t_START interval
is generated by an internal oscillator and counters. At the
end of t_START, this oscillator is powered down to reduce
overall power consumption.
Figure 1. Fan Speed Control Application
Proper sequencing of the /FS[2:0] and /SHDN signals is
performed by the MIC74’s internal logic state machine.
When activating the fan from the off state, the /FS[2:0]
lines change state first, then, after a delay equal to one-
half of t_START, the /SHDN pin is deasserted. Conversely,
when the fan is shutdown (zero is written to
FAN_SPEED), the /SHDN pin is deasserted first. The
/FS[2:0] lines are subsequently deasserted after a delay
of 1⁄2t_START. The internal oscillator is also powered down
following the t_START/2 interval at fan shut-down. These
timing relationships are illustrated in Figure 2.
Interrupt Generation
Assuming that any or all of the I/Os are configured as
inputs, the MIC74 will reflect the occurrence of an input
change in the corresponding bit in the status register,
STATUS. This action cannot be masked. An input
change will only generate an interrupt to the host if
interrupts are properly configured and enabled.
The MIC74 can operate in either polled mode or interrupt
mode. In the case of polled operation, the host
periodically reads the contents of STATUS to determine
the device state. The act of reading STATUS clears its
contents. Repeating events which have occurred since
the last read from STATUS will not be discernable to the
host.
Interrupts are only generated if the global interrupt enable
bit, IE, in the DEV_CFG register is set. The /ALERT
signal will be asserted (driven low) when an interrupt is
generated. The MIC74 expects to be interrogated using
the ARA when it has generated an interrupt output. Once
it has successfully responded to the ARA (Alert
Response Address), the /ALERT output will be
deasserted. The contents of the status register will not be
cleared until it is read using a read byte operation.
If a given system does not wish to use the SMBus ARA
protocol for reporting interrupts, the system may simply
poll the contents of the status register after detecting an
interrupt on /ALERT. This action will clear the contents of
STATUS and cause /ALERT to be deasserted. Reading
the status register is an acceptable substitute for using
the ARA protocol. Presumably, however, it will involve
higher system overhead since all the devices on the bus
must be polled to determine which one generated the
interrupt.
September 30, 2014
10
Revision 3.0