MIC5163_09 Datasheet, PDF (12/15 Pages) Micrel Semiconductor – Dual Regulator Controller for DDR3 GDDR3/4/5 Memory Termination

Micrel, Inc.
P_D = (V_DDQ − V_TT) × I_SOURCE
Where I_source is the average source current. Power
dissipation for the low-side MOSFET is as follows:
P_D = V_TT × I_SINK
Where I_sink is the average sink current.
In a typical 3.5A peak DDR3 circuit, power considera-
tions for MOSFET selection would occur as follows.
P_D = (V_DDQ −V_TT) × I_SOURCE
P_D = (1.5V −0.75V) × 1.75A
P_D = 1.3125 W
This typical DDR3 application would require both high-
side and low-side N-Channel MOSFETs to be able to
handle 1.3125 Watts each. In applications where there is
excessive power dissipation, multiple N-Channel
MOSFETs may be placed in parallel. These MOSFETs
will share current, distributing power dissipation across
each device.
The maximum MOSFET die (junction) temperature limits
maximum power dissipation. The ability of the device to
dissipate heat away from the junction is specified by the
junction-to-ambient (θ_JA) thermal resistance. This is the
sum of junction-to-case (θ_JC) thermal resistance, case-
to-sink (θ_CS) thermal resistance and sink-to-ambient
(θ_SA) thermal resistance;
θ_JA = θ_JC + θ_CS + θ_SA
In our example of a 3.5A peak DDR3 termination circuit,
we have selected a D-pack N-Channel MOSFET that
has a maximum junction temperature of 150°C. The
device has a junction-to-case thermal resistance of
1.5°C/W. Our application has a maximum ambient
temperature of 60°C. The required junction-to-ambient
thermal resistance can be calculated as follows:
θ _JA
=
T_J − T_A
P_D
Where T_J is the maximum junction temperature, T_A is the
maximum ambient temperature and P_D is the power
dissipation.
In our example:
θ _JA
=
T_J − T_A
P_D
θ _JA
=
150°C − 60°C
1.3125W
MIC5163
θ _JA
=
68.57 ^°C
W
This shows that our total thermal resistance must be
better than 68.57°C/W. Since the total thermal
resistance is a combination of all the individual thermal
resistances, the amount of heat sink required can be
calculated as follows:
θ_SA = θ_JA − (θ_JC + θ_CS)
In our example:
θ_SA = θ_JA − (θ_JC + θ_CS)
θ _SA
=
68.57 ^°C
W
− ⎜⎛1.5 ^°C
⎝^W
+ 0.5 ^°C ⎟⎞
W_⎠
θ _SA
=
66.57
°C
W
In most cases, case-to-sink thermal resistance can be
assumed to be about 0.5°C/W.
The DDR3 termination circuit for our example, using 2 D-
pack N-Channel MOSFETs (one high side and one on
the low side) will require at least a 43°C/W heat sink per
MOSFET. This may be accomplished with an external
heat sink or even just the copper area that the MOSFET
is soldered to. In some cases, airflow may also be
required to reduce thermal resistance.
MOSFET Gate Threshold
N-Channel MOSFETs require an enhancement voltage
greater than its source voltage. Typical N-Channel
MOSFETs have a gate-source threshold (V_GS) of 1.8V
and higher. Since the source of the high side N-Channel
is connected to V_TT, the MIC5163 V_CC pin requires a
voltage equal to or greater than the V_GS voltage. For
example, our DDR3 termination circuit has a V_TT voltage
of 0.75V. For an N-Channel that has a V_GS rating of
2.5V, the V_CC voltage can be as low as 3.25V. With an
N-Channel that has a 4.5V V_GS, the minimum V_CC
required is 5.25V. Although these N-Channels are driven
below their full enhancement threshold, it is
recommended that the V_CC voltage has enough margin
to be able to fully enhance the MOSFETs for large signal
transient response. In addition, low gate thresholds
MOSFETs are recommended to reduce the V_CC
requirements.
April 2009
12
M9999-042209-A