MIC5163_09 Datasheet, PDF(10/15 Page) Micrel Semiconductor – Dual Regulator Controller for DDR3 GDDR3/4/5 Memory Termination

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MIC5163_09 Datasheet, PDF (10/15 Pages) Micrel Semiconductor – Dual Regulator Controller for DDR3 GDDR3/4/5 Memory Termination

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Micrel, Inc.

Application Information

Synchronous Dynamic Random Access Memory

(SDRAM) has continually evolved over the years to keep

up with ever-increasing computing needs. The latest

addition to SDRAM technology is DDR3 SDRAM. DDR3

SDRAM is the third generation of the DDR SDRAM

family and offers improved power savings, higher data

bandwidth and enhanced signal quality with multiple on-

die termination (ODT) selection. In DDR3 SDRAM the

values of the ODT are based on the value of an external

resistor. In addition to using this external resistor for

setting the ODT value, it is also used for calibrating the

ODT value so that it maintains its resistance value to

within a 10% tolerance.

To improve signal integrity and support higher frequency

operations, the JEDEC committee defined a fly-by

termination scheme used with the clocks, the command

bus and address bus signals. The fly-by topology

reduces simultaneous switching noise (SSN) by

deliberately causing flight-time skew between the data

and strobes at every DRAM as the clock, address and

command signals traverse the DIMM.

The DDR3 SDRAM uses a programmable impedance

output buffer. Currently, there are two drive strength

settings, 34â¦ and 40â¦. The 40â¦ drive strength setting is

currently a reserved specification defined by JEDEC, but

available on the DDR3 SDRAM.

FPGA

DDR3 DIMM

DDR3 Component

Driver

Receiver

VREF = 0.75V

3â Trace Length

VREF = 0.75V

Driver

Receiver

Driver

Receiver

FPGA

DDR3 DIMM

DDR3 Component

VREF = 0.75V

3â Trace Length

VREF = 0.75V

Driver

Receiver

Figure 3. Dynamic OCT between Stratix III/IV

FPGA Devices

The MIC5163 is a high performance linear controller that

utilizes scalable N-Channel MOSFETs to provide

JEDEC compliant bus termination. Termination is

achieved by dividing down the VDDQ voltage by half to

provide the reference (VREF) voltage. An internal error

amplifier compares the termination voltage (VTT) and

VREF, controlling two external N-Channel MOSFETs to

sink and/or source current to maintain a termination

voltage (VTT) equal to VREF. The N-Channels receive

their enhancement voltage from a separate VCC pin on

the device. Although the general discussion is focused

MIC5163

on DDR3, the MIC5163 is also capable of providing bus

terminations for DDR, DDR2 and GDDR3/4/5.

VDDQ

The VDDQ pin on the MIC5163 provides the source

current through the high side N-Channel and the

reference voltage to the device. The MIC5163 can

operate at VDDQ voltages as low as 0.75V. Due to the

possibility of large transient currents being sourced from

this line, significant bypass capacitance will increase

performance by improving the source impedance at

higher frequencies. Since the reference is simply VDDQ/2,

perturbations on the VDDQ will also appear at half the

amplitude on the reference. For this reason, low ESR

capacitors such as ceramics or Oscons are

recommended on VDDQ.

VTT

VTT is the actual termination point. VTT is regulated to

VREF. Due to high speed signaling, the load current seen

by VTT is constantly changing. To maintain adequate

large signal transient response, Oscons and ceramics

are recommended on VTT. The proper combination and

placement of the Oscon and ceramic capacitors is

important to reduce both ESR and ESL such that high-

current high-speed transients do not exceed the dynamic

voltage tolerance requirement of VTT. The Oscon

capacitors provide bulk charge storage while the smaller

ceramic capacitors provide current during the fast edges

of the bus transition. Using several smaller ceramic

capacitors distributed near the termination resistors is

typically important to reduce the effects of PCB trace

inductance.

VREF

Two resistors dividing down the VDDQ voltage provide

VREF (Figure 5). The resistors are valued at around

17kâ¦. A minimum capacitor value of 120pF from VREF to

ground is required to remove high frequency signals

reflected from the source. Large capacitance values

(>1500pF) should be avoided. Values greater than

1500pF slow down VREF and detract from the reference

voltageâs ability to track VDDQ during high speed load

transients.

VDDQ = 1.2V

MIC5163

VCC = 5V

VDDQ

VCC HSD

SUD50N02-06P

VTT = 0.6V

100ÂµF 100ÂµF

6.3V 6.3V

1ÂµF

10V

120pF

LSD

VREF COMP

GND FB

220pF

100ÂµF

6.3V

100ÂµF

6.3V

GND

Figure 4. MIC5163 as a DDR3 Memory Termination Device

for 7A Application

April 2009

M9999-042209-A

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