PL502-35 Datasheet, PDF (1/10 Pages) Micrel Semiconductor – 750kHz – 800MHz Low Phase Noise Multiplier VCXO

PL502-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise ICs
FEATURES
PIN CONFIGURATION
 Selectable 750kHz to 800MHz range
(Top View)
 Low phase noise output (@ 10kHz frequency off-
set, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz)
 LVCMOS (PL502-37), LVPECL (PL502-35 and
PL502-38) or LVDS (PL502-39) output
 12MHz to 25MHz crystal input
 No external load capacitor or varicap required.
 Output Enable selector
 Wide pull range (±200 ppm)
 Selectable /16 to x32 frequency divider/multiplier
 3.3V operation
 Available in 16-Pin TSSOP or 16-pin 3x3mm QFN
GREEN/RoHS compliant packages
VDD 1
XIN 2
XOUT 3
SEL3^ 4
SEL2^ 5
OE 6
VCON 7
GND 8
1
6
SEL0^
1
5
SEL1^
1
4
GND
1
3
CLKC
1
2
VDD
1
1
CLKT
1
0
GND
9 GND
TSSOP-16L
^: Internal pull-up
*: On 3x3 package, PL502-35/-38 do not have SEL0 available: Pin 10
is VDD, pin 11 is GND. However, PL502-37/-39 have SEL0 (pin 10),
and pin11 is VDD. See pin assignment table for details.
DESCRIPTION
The PL502-35 (LVPECL with inverted OE), PL502-37
(LVCMOS), PL502-38 (LVPECL), and PL502-39
(LVDS) are high performance and low phase noise
VCXO IC chips. They provide phase noise perfor-
mance as low as –125dBc at 10kHz offset (at
155MHz), by multiplying the input crystal frequency up
to 32x. The wide pull range (±200 ppm) and very low
jitter make them ideal for a wide range of applications,
including SONET/SDH and FEC. They accept funda-
mental parallel resonant mode crystals from 12MHz to
25MHz.
XOUT
SEL3^
SEL2^
OE
12
13
11 10
9
8
14 _PL502-3x 7
15
6
16
5
123 4
GND
CLKC
VDD
CLKT
QFN-16L
BLOCK DIAGRAM
SEL[3:0]
VCON
XIN
XOUT
Oscillator
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
CLKC
CLKT
PL502-3x
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
PL502-38
PL502-35
PL502-37
PL502-39
0 (Default) Output enabled
1
Tri-state
0
Tri-state
1 (Default) Output enabled
OE input: Logical states defined by LVPECL levels for PL502-38
Logical states defined by LVCMOS levels for PL502-37/-39
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 4/15/13 Page 1