TH8061 Datasheet, PDF (9/36 Pages) Melexis Microelectronic Systems – Voltage Regulator with integrated LIN Transceiver

TH8061
Voltage Regulator with integrated LIN Transceiver
Parameter
Symbol
Condition
Min
Typ
Max Unit
LIN BUS parameter according to LIN Spec. Rev. 2.0
Conditions:
VSUP =7.0V to 18V; BUS loads: 1kΩ/1nF;660Ω/6.8nF;500Ω/10nF
TxD signal: tBit = 50µs, twH = TwL = tBit; trise = tfall < 100ns
Minimal recessive bit time ^{[2] [3]}
trec(min)
40
50
58 µs
Maximum recessive bit time ^{[2] [3]}
trec(max)
40
50
58 µs
Dyty cycle 1
D1
D1 = trec(min) / (2*tBit)
0.396
Dyty cycle 2
D2
D2 = trec(max) / (2*tBit)
0.581
[1] No production test, guaranteed by design and qualification
[2] See chapter 2.5 Timing Diagrams
[3] See chapter 2.6 Test Circuit for Dynamic and Static Characteristics
2.5 Timing Diagrams
50%
TxD
V_BUS
t_{df_TXD}
95%
100%
BUS
50%
RxD
0%
50%
t_{df_RXD}
t_{dr_TXD}
50%
5%
t_{dr_RXD}
Figure 2 - Timing diagram for propagation delay acc. to LIN 1.3 and 2.0
TH8061 – Datasheet
3901008061
Page 9 of 36
June 2004
Rev 007