MLX71120 Datasheet, PDF (5/30 Pages) Melexis Microelectronic Systems – 300 to 930MHz FSK/FM/ASK Receiver

1.3 Block Diagram
MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
3645
9
10
11
12 13 27 24
VEE
2
LNAI1 _LNA1
1
LNASEL
32
LNAI2 _LNA2
8
VEE
7
RFSEL
31
TEST
26
SEQ
BIAS
MIX1
MIX2
IFA
LO1
LO2
N1
counter
VCO
N2
counter
PFD
RO
LF
CP
30
25
14
17
16
100k 100k
DFO
ASK
OA1
18
FSK
SW1
FSK
DEMOD
PKDET+
20
PDP
PKDET_
PDN
21
SW2
DIV 8
28
15
22
OA2
19
NCF ^DTAO
29
CINT
23
Fig. 1: MLX71120 block diagram
PRELIMINARY ^{The MLX71120 receiver IC consists of the following building blocks:}
• PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2.
The PLL SYNTH consists of a fully integrated voltage-controlled oscillator (VCO), a distributed feedback
divider chain (N1,N2), a phase-frequency detector (PFD) a charge pump (CP), a loop filter (LF) and a
crystal-based reference oscillator (RO).
• Two low-noise amplifiers (LNA1, LNA2) for high-sensitivity RF signal reception
• First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)
• Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF
• IF amplifier (IFA) to provide a high voltage gain and an RSSI signal output
• FSK demodulator (FSK DEMOD)
• Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively
• Positive (PKDET+) and negative (PKDET-) peak detectors
• Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak
detection mode.
• Noise cancellation filter (NCF)
• Sequencer circuit (SEQ) and biasing (BIAS) circuit
• Clock output (DIV8)
39010 71120
Rev. 005
Page 5 of 30
Data Sheet
Feb/08