MLX71120 Datasheet, PDF (4/30 Pages) Melexis Microelectronic Systems – 300 to 930MHz FSK/FM/ASK Receiver

MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
1 Theory of Operation
1.1 General
The MLX71120 receiver architecture is based on a double-conversion super-heterodyne approach. The two
LO signals are derived from an on-chip integer-N PLL frequency synthesizer. The PLL reference frequency
is derived from a crystal (XTAL). As the first intermediate frequency (IF1) is very high, a reasonably high
degree of image rejection is provided even without using an RF front-end filter. At applications asking for
very high image rejections, cost-efficient RF front-end filtering can be realized by using a SAW filter in front
of the LNA. The second mixer MIX2 is an image-reject mixer.
The receiver signal chain is setup by one (or two) low noise amplifier(s) (LNA1, LNA2), two down-conversion
mixers (MIX1, MIX2) and an external IF filter with an on-chip amplifier (IFA). By choosing the required modu-
lation via an FSK/ASK switch (at pin MODSEL), either the on-chip FSK demodulator (FSK DEMOD) or the
RSSI-based ASK detector is selected. A second order data filter (OA1) and a data slicer (OA2) follow the
demodulator. The data slicer threshold can be generated from the mean-value of the data stream or by
means of the positive and negative peak detectors (PKDET+/-). A digital post-processing of the sliced data
signal can be performed by a noise cancellation filter (NCF) building block.
The dual LNA configuration can be used for antenna space diversity or antenna frequency diversity or to
setup an LNA cascade (to further improve the input sensitivity). The two LNAs can also be setup to feed the
RF signal differentially.
PRELIMINARY ^{A sequencer circuit (SEQ) controls the timing during start-up. This is to reduce start-up time and to minimize}
power dissipation.
A clock output, which is a divide-by-8 version of the crystal oscillator signal, can be used to drive a microcon-
troller. The clock output is open drain and gets activated through a load connected to positive supply.
1.2 Technical Data Overview
ˆ Input frequency ranges: 300 to 470MHz
610 to 930MHz
ˆ Power supply range: 2.1 to 5.5V
ˆ Temperature range: -40 to +125°C
ˆ Shutdown current: 50 nA
ˆ FSK deviation range: ±10kHz to ±100kHz (WB)
±2kHz to ±10kHz (NB)
ˆ Image rejection:
65dB 1^st IF (with external RF front-end filter)
25dB 2^nd IF (internal image rejection)
ˆ Operating current: 6.5 to 8.1mA
ˆ Maximum data rate: 50kps RZ (bi-phase) code,
ˆ FSK input sensitivity: -108dBm* (WB, 433MHz)
100kps NRZ
-112dBm* (NB, 433MHz)
ˆ Spurious emission: < -54dBm
ˆ ASK input sensitivity: -113dBm* (WB, 433MHz) ˆ Linear RSSI range: > 70dB
ˆ Selectable IF2 frequency: 10.7MHz or 455kHz
ˆ Crystal reference frequency: 16 to 27MHz
ˆ MCU clock frequency: 2.0 to 3.4MHz
* at 4kbps NRZ, BER = 3⋅10^-3, without SAW front-end-filter loss
WB – wideband (180kHz bandwidth at IF2=10.7MHz)
NB – narrowband (20kHz bandwidth at IF2=455kHz)
39010 71120
Rev. 005
Page 4 of 30
Data Sheet
Feb/08