MLX71120 Datasheet, PDF (11/30 Pages) Melexis Microelectronic Systems – 300 to 930MHz FSK/FM/ASK Receiver

MLX71120
300 to 930MHz
FSK/FM/ASK Receiver
1.14.1 Averaging Detection Mode
The simplest configuration is the averaging or RC inte-
gration method. Here an on-chip 100kΩ resistor to-
gether with an external slicer capacitor (CSL) are form-
ing an RC low-pass filter. This way the threshold voltage
automatically adjusts to the mean or average value of
the analog input voltage.
To create a stable threshold voltage, the cut-off fre-
quency of the low pass has to be lower than the lowest
signal frequency.
CSL ≥ ^τAVG
100k
τ _AVG
=
1.5
R _RZ
data
filter
SLCSEL
PKDET+ ^{data slicer}
PDP
S4
S1
100k
S2
switches S3 _VCC
PKDET_
S5
S6
SLC
CSL
PDN
A long string of zeros or ones, like in NRZ codes, can
cause a drift of the threshold. That’s why a Manchester
or other DC-free coding scheme works best.
The peak detectors are disabled during averaging de-
tection mode, and the output pins PDP and PDN are
pulled to ground (S4, S6 are closed).
Fig. 6:
OA2
Control
logic
DTAO
CINT
Data path in averaging detection mode
PRELIMINARY ^{1.14.2 Peak Detection Mode}
Peak detection mode has a general advantage over
averaging detection mode because of the part attack
and slow release times. Peak detection should be used
for all non DC-free codes like NRZ. In this configuration
the threshold is generated by using the positive and
negative peak detectors. The slicer comparator thresh-
old is set to the midpoint between the high output and
the low output of the data filter by an on-chip resistance
divider. Two external capacitors (CP1, CP2) determine
the release times for the positive and negative enve-
lope. The two on-chip resistors provide a path for the
capacitors to discharge. This allows the peak detectors
data
filter
SLCSEL
PKDET+ ^{data slicer} _PDP
S4
CP1
S1
100k
S2
switches S3 _VCC
PKDET_
S5
SLC
CP2
PDN
to dynamically follow peak changes of the data filter
S6
output voltage. The attack times are very short due to
the high peak detector load currents of about 500uA.
The decay time constant mainly depends on the longest
OA2
Control
logic
DTAO
time period without bit polarity change. This corre-
CINT
sponds to the maximum number of consecutive bits with
the same polarity (N_MAX).
Fig. 7: Data path in peak detection mode
CP1/2 ≥ ^{τ DECAY}
100k
τ _DECAY
=
N _MAX
R _NRZ
If the receiver is in shutdown mode and peak detection mode is selected then the peak detectors are dis-
abled and the output of the positive peak detector (PDP) is connected to VEE (S4 is closed) and the output
of the negative peak detector (PDN) is connected to VCC (S5 is closed). This guarantees the correct biasing
of CP1 and CP2 during start-up
39010 71120
Rev. 005
Page 11 of 30
Data Sheet
Feb/08