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TH3122 Datasheet, PDF (4/14 Pages) Melexis Microelectronic Systems – K-Bus Transceiver with integrated Voltage Regulator | |||
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TH3122
K-Bus Transceiver with integrated Voltage Regulator
Bit Compare
If the signals at the pin TxD and the pin BUS within
a specified time tbc are not identical, the
transmission will be interrupted.
If both signals at TxD and BUS are âHighâ within
the time tena the transmission will be enabled. The
bit-compare-function is active when the pin SEN/
STA is open (not overwritten).
Using this pin as an input the transmission path
can be overwritten (independent of bit-compare
and constant-low function):
SEN/STA=â0â
forcing the transmission path free
SEN/STA=â1â
disable the transmission path
Figure 5 - Bit Compare Pulse Diagram
SEN/STA
Constant Low Switch Off
A falling edge at pin TxD (from â1â to â0â) starts the
internal constant low timer (SEN/STA open).
If the low level â0â is valid for the time tlow the
transmission unit of the TH3122 will be disabled.
The receive unit is still active. A high level â1â at
TxD with a minimum pulse width of trec resets the
constant low timer.
Transmitting is not possible until TxD and BUS is
High for the time tena.
t < trec
TxD
The pin SEN/STA is bidirectional. Used as an
output the pin indicates whether the transmit-path
is enabled or disabled:
SEN/STA =â0â
transmission path is enabled
SEN/STA =â1â
transmission path is disabled
SEN/STA
tlow
tena
Figure 6 - Constant Low Pulse Diagram
Linear Regulator and Controlling Functions
Regulator
The TH3122 has an integrated linear regulator with an
output voltage of 5V 展 2% and an output current of max.
100mA. The regulator is switched on or off with a signal
on the EN pin or wakes up with a BUS signal.
Initialization
The initialization is started if the power supply is switched
on, or after the temperature limitation has switched off
the regulator or in case of BUS traffic (wake up).
voltage level on the VTR pin (see table VTR
Programming). After tRES a rising edge on the RESET
output is generated (see figure 7 - Initialization).
The regulator is active and can only be switched off with
a falling edge on EN. The regulator remains with
EN=high in active mode and therefore the VCC voltage is
also active.
If the VCC voltage level is higher than VRESEIN, the reset
time tRES is started. This reset time is determined by the
3901003122
Rev 004
Page 4
Dec/04
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