MLX90288 Datasheet, PDF (12/19 Pages) Melexis Microelectronic Systems – SMD Programmable Linear Hall Sensor IC Featuring Analog Ratiometric Output

MLX90288
SMD Programmable Linear Hall Sensor IC
Featuring Analog Ratiometric Output
6.3.5 SECONDORDERTC
• Chooses between linear gain compensation over temperature (cleared) and ROM based 2^nd order
compensation (set) as described under Section 5.5
6.3.6 TEMPOFF[9:0]
• Will be calibrated at MLX production
• Defines the offset of the GainMag temperature compensation as described under Section 5.5
6.3.7 TEMPTC[7:0]
• Will be calibrated at MLX production
• Defines the slope of the GainMag temperature compensation as described under Section 5.5
6.3.8 CLPLow[8:0]
• Low clamp level programmability range from 0% to 50% of VDD
• Resolution is 1/4^th of the outDAC resolution, i.e. 0.098% of VDD
6.3.9 CLPHigh[9:0]
• High clamp level programmability range from 0% to 100% of VDD
• Resolution is 1/4^th of the outDAC resolution, i.e. 0.098% of VDD
6.3.10 ROUGHGAIN[1:0]
• These 2 bits control the gain of the MAIN AMPLIFIER
6.3.11 ATTN2P5
• Enables the attenuation in the analog chain by a factor of 4.5
6.3.12 FINEGAIN[12:0]
• Sign-magnitude 13bit digital fine gain (not 2’s complement!)
• The code 1024 (400h) corresponds to a gain of 1
• The code 5120 (1400h) corresponds to a gain of -1
• The MSB is a sign bit
• FINEGAIN range is therefore from -4095 (1FFFh) to +4095 (FFFh), which corresponds to a gain
range of -3.999 to +3.999
6.3.13 YA[13:0]
• Output offset programming, not gain dependent
• Defines the offset on the output in case no field is applied, inside a range of -200%Vdd to +200%
Vdd with the 12-bit resolution of the output DAC, i.e. 0.0244% of VDD
6.3.14 CSTID[15:0]
• Customer ID bits for traceability
3901090288
Rev 002
Page 12 of 19
May/12