MLX71121_15 Datasheet, PDF (11/29 Pages) Melexis Microelectronic Systems – FSK/OOK Receiver

MLX71121
300 to 930MHz
FSK/OOK Receiver
1.15.1 Averaging Detection Mode
The simplest configuration is the averaging or RC inte-
gration method. Here an on-chip 100k resistor togeth-
er with an external slicer capacitor (CSL) are forming an
RC low-pass filter. This way the threshold voltage au-
tomatically adjusts to the mean or average value of the
analog input voltage.
To create a stable threshold voltage, the cut-off fre-
quency of the low pass has to be lower than the lowest
signal frequency.
CSL

τ _AVG
100k
τ _AVG

1.5
R _RZ
A long string of zeros or ones, like in NRZ codes, can
cause a drift of the threshold. That’s why a Manchester
or other DC-free coding scheme works best.
The peak detectors are disabled during averaging de-
tection mode, and the output pins PDP and PDN are
pulled to ground (S4, S6 are closed).
data
filter
SLCSEL
data slicer
PKDET+
PDP
S4
S1
100k _S2
switches S3 _VCC
PKDET_
S5
S6
SLC
CSL
PDN
OA2
Control
logic
DTAO
CINT
Fig. 7: Data path in averaging detection mode
1.15.2 Peak Detection Mode
Peak detection mode has a general advantage over
averaging detection mode because of the part attack
and slow release times. Peak detection should be used
for all non-DC-free codes like NRZ. In this configuration
the threshold is generated by using the positive and
negative peak detectors. The slicer comparator thresh-
old is set to the midpoint between the high output and
the low output of the data filter by an on-chip resistance
divider. Two external capacitors (CP1, CP2) determine
the release times for the positive and negative enve-
lope. The two on-chip resistors provide a path for the
capacitors to discharge. This allows the peak detectors
to dynamically follow peak changes of the data filter
output voltage. The attack times are very short due to
the high peak detector load currents of about 500uA.
The decay time constant mainly depends on the longest
time period without bit polarity change. This corre-
sponds to the maximum number of consecutive bits with
the same polarity (N_MAX).
CP1/2

τ _DECAY
100k
τ _DECAY

N _MAX
R _NRZ
data
filter
SLCSEL
data slicer
PKDET+
PDP
S4
S1
100k _S2
switches S3 _VCC
PKDET_
S5
S6
CP1
SLC
CP2
PDN
OA2
Control
logic
DTAO
CINT
Fig. 8: Data path in peak detection mode
If the receiver is in shutdown mode and peak detection mode is selected then the peak detectors are disa-
bled and the output of the positive peak detector (PDP) is connected to VEE (S4 is closed) and the output of
the negative peak detector (PDN) is connected to VCC (S5 is closed). This guarantees the correct biasing of
CP1 and CP2 during start-up.
39010 71121
Rev. 012
Page 11 of 29
Data Sheet
Mar/15