MA014B Datasheet, PDF (8/14 Pages) Megawin Technology Co., Ltd – Single chip 8-bit CPU

Divider (The example is base on 3. 579545MHz)
Name
/256 /128
/64
/32
/16
DIVlow
13984 227968 55937 111875 223750
Name
/4096
DIVhigh
-
-
-
-
874
/8
447500
/2048
1748
/4
895000
/1024
3496
Unite:Hz
/2
RW
1790000 _{- -}
/512 R W
6992 _{- -}
The time-out period is obtained by the equation: 4096/OSC.
The DIV flag will be set when 4096/OSC or 256 /OSC (selected by DIVsel) is met.
Cloc
k
Clock/x
To TM0
Divider (12-bit)
R
Clock/4096
Pulse
generator
Sys_rst or
CPU STOP=1
Data
Bus
Data bus_bit4
Write
EVTclr
S
D
Q
CR
Sys_rst
DIVevt
Read
EVTflag
Divider Architecture
Watchdog Timer (WDT, The example is base on 3.579545MHz)
Name
(F_OSC /4096)/16
WDT
----
55
109
218
Unite:Hz
RW
437
--
The watchdog timer time-out period is obtained by the equation: (F_OSC / 4096)/16
Before watchdog timer time-out occurs, the program must clear the 4-bit WDT timer by writing 0 to
EVTclr.5. WDT overflow will cause system reset and set EVTflag.5 to high.
Clock/4096
16
R
Write EVTclr
Data bus_bit5=0
Over flow
detection
Pulse
generator
WDT reset
Data
bus_bit5
DS
Q
Write EVTclr
CR
Hard_rst
WDTevt
Watchdog Block Diagram
MEGAWIN
MA014B Series Technical Summary
8