MA014B Datasheet, PDF (6/14 Pages) Megawin Technology Co., Ltd – Single chip 8-bit CPU

Interrupt
The MA014B provides 3 interrupt sources: port0, timer0 and divider. Each of the
Interrupt sources can be individually enabled or disabled by setting or clearing a bit in the IRQen
Three interrupts share the interrupt vector FFFEH/FFFFH.
DIV interrupt: IRQen.4 (DIVen) = 1 and DIVevt = 1.
P0 interrupt: IRQen.0 (P0en) = 1 and P0evt = 1.
TM0 interrupt IRQen.3 (TM0en) = 1 and TM0evt = 1.
Interrupt Vectors
Vector Address
Item
FFFCH, FFFDH RESET
“
WDT
“
LVR
FFFEH, FFFFH
P0
“
DIV
“
TM0
Flag
None
WDTirq
None
P0irq
DIVirq
TM0irq
Properties
Ext.
Int.
Ext.
Ext.
Int.
Int.
Memo
Initial reset
Watchdog reset
Low voltage reset
Port P0 interrupt vector
Divider carry out interrupt
TM0 underflow interrupt
IRQen.P0en
P0evt
IRQen.TM0e
n
TM0evt
IRQen.DIVen
DIVevt
Interrupt Architecture
Interrupt
(to CPU)
IRQ enable flag
Address Name Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2 Bit 1
00E2H IRQen
-
-
-
DIVen TM0en
-
-
Program can enable or disable the ability of triggering IRQ through this register.
0: Disable (default "0" at initialization)
1: Enable
P0en: Falling edge occurs at port 0 (input mode)
TM0en: Timer0 underflow occurred.
DIVen: DIV interrupt frequency occurred
Bit 0 R W
P0en - 
MEGAWIN
MA014B Series Technical Summary
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