MA014B Datasheet, PDF (7/14 Pages) Megawin Technology Co., Ltd – Single chip 8-bit CPU

IRQ status flag
Address Name Bit 7 Bit 6
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00E3H EVTflag -
LVD
WDT
DIV
TM0
-
-
P0
When IRQ occurs, program can read this register to know which source triggering IRQ.
RW
-
P0:P0 interrupt flag. Set by falling edge on any pin of port0. Clear by software.
DIV: Divider interrupts flag. Clear by software.
WDT: WDT time-out flag. Clear flag and WDT counter by software.
TM0: Timer0 underflow flag and the flag clear by software.
LVD: Low voltage detected. 1:VDD is under 2.1V. 0:VDD is above 2.1V. It is set by hardware and
read only. (Note: The maximum LVD voltage will below 2.4V)
IRQ clear flag
Address Name
Bit 7
00E3H
EVTclr
-
Bit 6
-
Bit 5
Bit 4
WDT
DIV
Bit 3 Bit 2
TM0
-
Bit 1
-
Bit 0
P0
RW
-
Program can clear the interrupt event by writing ‘0’ into the corresponding bit.
Main Clock Manager
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
00E0H MCLKmgr
-
-
- DIVsel -
-
Bit 1
-
Bit 0 R W
OSCen - 
OSCen: 0:The oscillator is free run. 1:The oscillator is frozen (stop mode).
When system clocks stop oscillating. The uC can be awakened from stop mode by 3-ways:
port 0 interrupt, hardware reset, or power-on reset.
DIVsel: Divider interrupt frequency selector
0: The Fosc/4096 interrupt frequency is selected
1: The Fosc/256 interrupt frequency is selected
OSCI
OSCO
Crystal
oscillator
Clock
Data bus_bit0
Write MCLK
Interrupt
Sys_rst
D
Q
CR
OSCen
Oscillator Architecture
Reset OK
Address Name
00E1H RESOK
Bit 7 Bit 6 Bit 5
RK7 RK6 RK5
Bit 4
RK4
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
RW
-
RESOK (Reset OK): If the device reset OK and work well, must write #$90 into this register.
For example:
Program_start: LDA #10010000b
STA $E1
MEGAWIN
MA014B Series Technical Summary
7