MG82FG5B32 Datasheet, PDF (215/273 Pages) Megawin Technology Co., Ltd – Flexible IAP size by software configured

25.2. ADC Operation
ADC has a maximum conversion speed of 200 ksps. The ADC conversion clock is a divided version of the
system clock or the timer overflow rate of S1BRG and Timer 0, determined by the ADCKS2~0 bits in the
ADCFG0 register. The ADC conversion clock should be no more than 6 MHz.
After the conversion is complete (ADCI is high), the conversion result can be found in the ADC Result Registers
(ADCDH, ADCDL). For single ended conversion, the result is
ADC Result =
V_IN x 1024
VDD Voltage
25.2.1. ADC Input Channels
The analog multiplexer (AMUX) selects the inputs to the ADC, allowing any of the pins on Port 1 to be measured
in single-ended mode. The ADC input channels are configured and selected by CHS3~0 in the ADCON0 register
as described in Figure 25–1. The selected pin is measured with respect to GND.
25.2.2. Starting a Conversion
Prior to using the ADC function, the user should:
1) Turn on the ADC hardware by setting the ADCEN bit,
2) Select ADCMS to configure ADC for single-ended mode or fully-differential mode
3) Configure the ADC input clock by bits ADCKS2, ADCKS1 and ADCKS0,
4) Select the analog input channel by bits CHS3, CHS2, CHS1 and CHS0,
5) Configure the ADC voltage reference source
6) Configure the selected input (shared with P1) to the Analog-Input-Only mode by P1, P1M0 and P1AIO
registers, and
7) Configure ADC result arrangement using ADRJ bit.
Now, user can set the ADCS bit to start the A-to-D conversion. The conversion time is controlled by bits ADCKS2,
ADCKS1 and ADCKS0. Once the conversion is completed, the hardware will automatically clear the ADCS bit,
set the interrupt flag ADCI and load the 10 bits of conversion result into ADCH and ADCL (according to ADRJ bit)
simultaneously. If user sets the ADCS and selects the ADC trigger mode to S1BRG/Timer0 over flow or free-run,
then the ADC will keep conversion continuously unless ADCEN is cleared or configure ADC to manual mode.
As described above, the interrupt flag ADCI, when set by hardware, shows a completed conversion. Thus two
ways may be used to check if the conversion is completed: (1) Always polling the interrupt flag ADCI by software;
(2) Enable the ADC interrupt by setting bits EADC (in EIE1 register) and EA (in IE register), and then the CPU will
jump into its Interrupt Service Routine when the conversion is completed. Regardless of (1) or (2), the ADCI flag
should be cleared by software before next conversion.
25.2.3. ADC Conversion Time
The user can select the appropriate conversion speed according to the frequency of the analog input signal. The
maximum input clock of the ADC is 6MHz and it operates a fixed conversion time with 30 ADC clocks. User can
configure the ADCKS2~0 in ADCFG0 to specify the conversion rate. For example, if SYSCLK=12MHz and the
ADCKS = SYSCLK/2 is selected, then the frequency of the analog input should be no more than 200KHz to
maintain the conversion accuracy. (Conversion rate = 12MHz/2/30 = 200KHz.)
25.2.4. I/O Pins Used with ADC Function
The analog input pins used for the A/D converters also have its I/O port ‘s digital input and output function. In
order to give the proper analog performance, a pin that is being used with the ADC should have its digital output
as disabled. It is done by putting the port pin into the input-only mode. And when an analog signal is applied to
MEGAWIN
MG82FG5BXX Data Sheet
215