MG82FG5B32 Datasheet, PDF (169/273 Pages) Megawin Technology Co., Ltd – Flexible IAP size by software configured

21. Two Wire Serial Interface (TWI0 and TWI1)
The Two-Wire Serial interface is a two-wire, bi-directional serial bus. It is ideally suited for typical microcontroller
applications. The MG82FG5BXX is embedded two independent hardware engine to service the Two-Wire Serial
Interface, TWI0 and TWI1. TWI1 is duplicated design from TWI0 with fully compatible control flow except different
SFR access page and different port pin. All TWI0 SFRs are accessed in SFR page 0 and its interface pins are
TWI0_SCL and TWI0_SDA. The SFRs of TWI1 are located in SFR page 1 with the two signals, TWI1_SCL and
TWI1_SDA.
The TWI0 protocol allows the systems designer to interconnect up to 128 different devices using only two bi-
directional bus lines, one for clock (TWI0_SCL) and one for data (TWI0_SDA). The TWI0 bus provides control of
TWI0_SDA (serial data), TWI0_SCL (serial clock) generation and synchronization, arbitration logic, and
START/STOP control and generation. The only external hardware needed to implement this bus is a single pull-
up resistor for each of the TWI0 bus lines. All devices connected to the bus have individual addresses, and
mechanisms for resolving bus contention are inherent in the TWI0 protocol.
Figure 21–1. TWI0 Bus Interconnection
VDD
Device 0
Device 1
Device 2 ……… Device n
TWI0_SDA
TWI0_SCL
The TWI0 bus may operate as a master and/or slave, and may function on a bus with multiple masters. The CPU
interfaces to the TWI0 through the following four special function registers: SICON configures the TWI0 bus;
SISTA reports the status code of the TWI0 bus; and SIDAT is the data register, used for both transmitting and
receiving TWI0 data. SIADR is the slave address register. And, the TWI0 hardware interfaces to the serial bus via
two lines: TWI0_SDA (serial data line) and TWI0_SCL (serial clock line).
Figure 21–2. TWI0 Block Diagram
CPU Write SIDAT
CPU Read SIDAT
CPU R/W SIADR
Output Shift
Register
Input Shift
Register
Slave Addr
Register
TWI0 Control
I/O
Control
TWI0_SDA
(P4.1/P6.1)
TWI0_SCL
(P4.0/P6.0)
SYSCLK
S1TOF
T0OF
/8
/16
/32
/64
/128
/256
S1TOF/6
T0OF/6
CR2
ENSI
STA
STO
SI
SICON
AA
CR1
CR0
SISTA
b7
b6
b5
b4
b3
b2
b1
b0
MEGAWIN
MG82FG5BXX Data Sheet
169