MA007A Datasheet, PDF (2/16 Pages) Megawin Technology Co., Ltd – 3-in-1 8-bit serial to parallel latch

General Description
The MA007 are high-speed Si-gate CMOS
devices. There are three groups 8-stage serial
shift register with a storage register and 3-state
outputs in MA007. The shift register and storage
register have separate clocks. Data is shifted on
the positive-going transitions of the SCLK input.
The data in each register is transferred to the
storage register on a positive-going transition of
the PCLK input. If both clocks are connected
together, the shift register will always be one clock
pulse ahead of the storage register. The shift
register has a serial input (DINx) and a serial
standard output (DOUTx) for cascading. It is also
provided with asynchronous reset (active LOW)
for all 8 stages shift register. The storage register
has 8 parallel 3-state bus driver outputs. Data in
the storage register appears at the output
whenever the output enable input (/OE) is LOW.
Pad Description
Pad No.
1
2
3
4
5, 6, 7
10, 9, 8
20 to 13
29 to 22
38 to 31
12, 30, 40
11, 21, 39, 41
Pad Name
/OE
PCLK
/SCLR
SCLK
DIN0, DIN1, DIN2
DOUT0, DOUT1, DOUT2
Q20 to Q27
Q10 to Q17
Q00 to Q07
VCC
GND
I/O
Description
I Output enable (active LOW)
I Parallel register clock input
I Serial register reset (active LOW)
I Shift register clock input
I Serial data input
O Serial data output
O Parallel data group 2 output
O Parallel data group 1 output
O Parallel data group 0 output
P Positive supply voltage
P Power ground (0 V)
2
MA007A Technical Summary
MEGAWIN