MX66L51235F Datasheet, PDF (68/107 Pages) Macronix International – 3V 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX66L51235F
9-29. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to minimum power consumption (the standby
current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction
to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are
ignored. When CS# goes high, it's only in deep power-down mode not standby mode. It's different from Standby
mode.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID being
reading out). When Power-down, or software reset command the deep power-down mode automatically stops, and
when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly at the
byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed.
As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode.
Figure 62. Deep Power-down (DP) Sequence (SPI Mode)
CS#
Mode 3
SCLK
Mode 0
SI
01234567
Command
B9h
t_DP
Stand-by Mode Deep Power-down Mode
Figure 63. Deep Power-down (DP) Sequence (QPI Mode)
CS#
t_DP
Mode 3
01
SCLK
Mode 0
Command
SIO[3:0]
B9h
Stand-by Mode Deep Power-down Mode
P/N: PM1832
REV. 1.0, MAY. 23, 2013
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