MX66L51235F Datasheet, PDF (56/107 Pages) Macronix International – 3V 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX66L51235F
9-21. Performance Enhance Mode Reset
To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle(8 clocks in 3-byte
address mode)/3FFh data cycle(10 clocks in 4-byte address mode), should be issued in 1I/O sequence. In QPI
Mode, FFFFFFFFh data cycle(8 clocks in 3-byte address mode)/FFFFFFFFFFh data cycle (10 clocks in 4-byte
address mode), in 4I/O should be issued.
If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care
when during SPI mode.
Figure 42. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI Mode)
CS#
Mode 3
SCLK _{Mode ̌}
SIO0
SIO1
SIO2
SIO3
Mode Bit Reset
for Quad I/O
̌1 2 3 4 5 6 7
FFh
Don’t Care
Don’t Care
Don’t Care
Mode 3
Mode ̌
Figure 43. Performance Enhance Mode Reset for Fast Read Quad I/O (QPI Mode)
CS#
Mode 3
SCLK _{Mode ̌}
Mode Bit Reset
for Quad I/O
̌1 2 3 4 5 6 7
SIO[3:0]
FFFFFFFFh
Mode 3
Mode ̌
P/N: PM1832
REV. 1.0, MAY. 23, 2013
56