MX25L6473E Datasheet, PDF (45/86 Pages) Macronix International – 64M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX25L6473E
9-21. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to en-
tering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down
mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is
not active and all Write/Program/Erase instructions are ignored. When CS# goes high, it's only in standby mode
not deep power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high.
The SIO[3:1] are don't care when during this mode.
Once the DP instruction is set, all instructions will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When
Power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is
in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of
instruction code has been latched-in); otherwise, the instruction will not be executed. As soon as Chip Select (CS#)
goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to
ISB2.
Figure 25. Deep Power-down (DP) Sequence (Command B9)
CS#
01234567
t_DP
SCLK
Command
SI
B9h
Stand-by Mode Deep Power-down Mode
P/N: PM1907
REV. 1.1, NOV. 06, 2013
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