MX25L6473E Datasheet, PDF (23/86 Pages) Macronix International – 64M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX25L6473E
9-5. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Be-
fore sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the
Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3,
BP2, BP1, BP0) bits to define the protected area of memory (as shown in "Table 2. Protected Area Sizes"). The
WRSR can reset the Status Register Write Disable (SRWD) bit, but has no effect on bit1 (WEL) and bit0 (WIP) of
the status register.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Regis-
ter data on SI→ CS# goes high.
Figure 6. Write Status Register (WRSR) Sequence (Command 01)
CS#
Mode 3
SCLK
Mode 0
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
command
01h
High-Z
Status
Register In
Configuration
Register In
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
MSB
P/N: PM1907
REV. 1.1, NOV. 06, 2013
23