MX25L6473E Datasheet, PDF (39/86 Pages) Macronix International – 64M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY

MX25L6473E
9-18. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device
programs only the last 256 data bytes sent to the device. The last address byte (the 8 least significant address
bits, A7-A0) should be set to 0 for 256 bytes page program. If A7-A0 are not all zero, transmitted data that
exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently
selected page. If the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the
request page and previous data will be disregarded. If the data bytes sent to the device has not exceeded 256,
the data will be programmed at the request address of the page. There will be no effort on the other data bytes of
the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on
SI→ at least 1-byte on data on SI→ CS# goes high.
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise, the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked out during the Page Program cycle is in progress. The WIP sets 1
during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit
is reset. If the page is protected by BP3~0 (WPSEL=0) or by individual lock (WPSEL=1), the array data will be
protected (no change) and the WEL bit will still be reset.
The SIO[3:1] are don't care when during this mode.
Figure 20. Page Program (PP) Sequence (Command 02)
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Command
24-Bit Address
Data Byte 1
SI
02h
23 22 21
321076543210
MSB
MSB
CS#
SCLK
SI
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte 256
7654321076543210
MSB
MSB
76543210
MSB
P/N: PM1907
REV. 1.1, NOV. 06, 2013
39