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9042 Datasheet, PDF (6/26 Pages) Maxwell Technologies – 12-Bit, 41 MSPS A/D Converter
12-Bit, 41 MSPS A/D Converter
9042
TABLE 5. 9042 AC ELECTRICAL CHARACTERISTICS1
(AVCC = DVCC = +5V ±5%; ENCODE & ENCODE = 41 MSPS; VREF TIED TO VOFFSET THROUGH 50 Ω; TA = -55°C TO +125°C)
PARAMETER
SYMBOL
CONDITION
SUBGROUPS
MIN
TYP
MAX
UNIT
Maximum Conversion Rate
Minimum Conversion Rate8
Aperature Delay
Aperature Uncertainty
ENCODE Pulse Width High
ENCODE Pulse Width Low
Output Delay
-55 to 125°C 9, 10, 11
41
MSPS
-55 to 125°C 9, 10, 11
5
MSPS
tA
25° C
9
Jitter
25° C
9
-250
ps
0.7
ps rms
25° C
9
10
ns
25° C
9
10
ns
tOD
-55 to 125°C 9, 10, 11
5
9
14
ns
1. All AC specifications tested by driving ENCODE and ENCODE differentially.
2. Analog input signal power at -1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed).
3. Analog input signal power at -1 dBFS; signal-to-noise and distorsion (SINAD) is the ratio of signal level to total noise + harmonics.
4. Analog input signal power at -1 dBFS; worst spur is the ratio of signal level to worst spur, usually limited by harmonics.
5. Analog input signal power swept from -20 dBFS to -95 dBFS; dither power = -32.5 dBm; dither circuit used on input signal SFDR is ratio of converter full scale to worst spur.
6. Tones at -7dBFS (F1 = 15.3 MHz, F2 = 19.5 MHz); two tone intermodualtion distortion (IMD) rejection is ratio or either tone to worst third order intermod product.
7. Both input tones swept from -20 to -95 dBFS; dither power = -32.5 dBm; dither circuit used on input signal two-tone spurious-free dynamic range (SFDR) is the ratio of converter full
scale to worst spur.
8. Guaranteed by design.
FIGURE 1. TIMING DIAGRAM
01.07.05 REV 7
All data sheets are subject to change without notice 6
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