9042 Datasheet, PDF (16/26 Pages) Maxwell Technologies – 12-Bit, 41 MSPS A/D Converter

12-Bit, 41 MSPS A/D Converter
9042
THEORY OF OPERATION
The 9042 analog-to-digital converter (ADC) employs a twostage subrange architecture. This design approach ensures
12-bit accuracy, without the need for laser trim, at low power. As shown in the functional block diagram, the 1 V p-p
SingleEnded analog input, centered at 2.4 V, drives a single-in to differential-out amplifier, A1. The output of A1 drives
the first track-and-hold, TH1. The high state of the ENCODE pulse places TH1 in hold mode. The held value of TH1 is
applied to the input of the 6-bit coarse ADC. The digital output of the coarse ADC drives a 6-bit DAC; the DAC is 12
bits accurate. The output of the 6-bit DAC is subtracted from the delayed analog signal at the input to TH3 to generate
a residue signal. TH2 is used as an analog pipeline to null out the digital delay of the coarse ADC. The residue signal
is passed to TH3 on a subsequent clock cycle where the signal is amplified by the residue amplifier, A2, and converted
to a digital word by the 7-bit residue ADC. One bit of overlap is used to accommodate any linearity errors in the coarse
ADC.
The 6-bit coarse ADC word and 7-bit residue word are added together and corrected in the digital error correction logic
to generate the output word. The result is a 12-bit parallel digital word which is CMOS-compatible, coded as twos com-
plement.
APPLYING THE 9042
Encoding the 9042
The 9042 is designed to interface with TTL and CMOS logic families. The source used to drive the ENCODE pin(s)
must be clean and free from jitter. Sources with excessive jitter will limit SNR (ref. Equation 1 under “Noise Floor and
SNR”).
Figure 19. Single-Ended TTL/CMOS Encode
01.07.05 REV 7
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