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97SD3248_06 Datasheet, PDF (4/40 Pages) Maxwell Technologies – 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks
1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
97SD3248
TABLE 4. DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V + 0.3V, VCCQ = 3.3V + 0.3V, TA = -55 TO 125°C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
TEST CONDITIONS
SUBGROUPS MIN
MAX
UNITS
Standby Current in non power down6
Standby Current in non power down7
( Input signal stable)
Active standby current in1,2,4
power down
Active standby current in power down
(input signal stable)2,5
Active standby power in non power
down1,2,6
Active standby current in non power
down ( input signal stable)2,7
Burst Operating Current1,2,8
CAS Latency = 2
CAS Latency = 3
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
CKE, CS = VIH
tCK = 12 ns
CKE = VIH
tCK = 0
CKE = VIL
tCK = 12 ns
CKE = VIL
tCK = 0
CKE, CS1-6 = VIH
tCK = 12 ns
CKE = VIH
tCK = 0
tCK = min
BL = 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
120 mA
54
mA
24
mA
18
mA
180 mA
90
mA
mA
660
870
Refresh Current3
ICC5
tRC = min
1, 2, 3
1320 mA
Self Refresh current9,10
ICC6
VIH>VCC - 0.2V
1, 2, 3
VIL < 0.2 V
18
mA
Input Leakage Current - CLK
ILI
0<VLI<VCC
1, 2, 3
-3
3
uA
Input Leakage Current - All Other
ILI
0<VLI<VCC
1, 2, 3
-6
6
uA
Output Leakage Current
ILO
0<VLO<VCC
1, 2, 3 -1.5
1.5
uA
Output high voltage
VOH
IOH = -4mA
1, 2, 3 2.4
V
Output low voltage
VOL
IOL = 4 mA
1, 2, 3
0.4
V
1. ICC1 depends on output load conditions when the device is selected. ICC1(max) is specified with the output open.
2. One Bank Operation
3. Input signals are changed once per clock.
4. After power down mode, CLK operating current.
5. After power down mode, no CLK operating current.
6. Input signals are changed once per two clocks.
7. Input signals for VIH or VIL are fixed.
8. Input signals are changed once per four clocks.
9. After self refresh mode set, self refresh current.
10.Use Self Refresh for temperatures less than 70 °C ONLY.
05.10.06 Rev 4
All data sheets are subject to change without notice 4
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