97SD3248_06 Datasheet, PDF (27/40 Pages) Maxwell Technologies – 1.5Gb SDRAM 8-Meg X 48-Bit X 4-Banks

1.5Gb (8-Meg X 48-Bit X 4-Banks) SDRAM
97SD3248
Read command to Write command Interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of
the same bank as the preceding read command, the write command can be performed after an interval of no
less than 1 clock. However, DQM must be set High so the output buffer becomes High-Z before data input.
READ to WRITE Command Interval (1)
READ to WRITE Command Interval (2)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no
less than 1 cycle, provided that the other bank is in the bank-active state. However, DQM must be set High
so that the output buffer becomes High-Z before data input.
05.10.06 Rev 4
All data sheets are subject to change without notice 27
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