MAX1661 Datasheet, PDF (9/16 Pages) Maxim Integrated Products – Active-Matrix Liquid Crystal Display AMLCD Supply

Active-Matrix Liquid Crystal Display
(AMLCD) Supply
Table 1. Switching Frequency Options
FPLL
IN
REF
GND
f_BPCLK
(kHz)
f_{DC-DC 1}
(kHz)
f_{DC-DC 2 MAX}
(kHz)
f_{DC-DC 1}:
f_BPCLK
f_{DC-DC 2 MAX}:
f_BPCLK
N*
40 to 72
640 to 1152
320 to 576
16:1
8:1
32
27 to 48
640 to 1152
320 to 576
24:1
12:1
48
20 to 36
640 to 1152
320 to 576
32:1
16:1
64
*See Figure 2
Fixed-frequency, current-mode operation ensures that
the switching noise exists only at the operating frequen-
cy and its harmonics. The switching frequency is phase
locked to the backplane clock input. Table 1 illustrates
the possible switching-frequency options.
DC-DC 2 Dual Outputs
DC-DC 2 uses a synchronized, fixed on-time PFM
architecture to provide the positive and negative output
voltages that allow the driver ICs to turn the TFT gates
on and off. When pulses occur, they are synchronized
to DC-DC 1, thereby minimizing converter interactions
and subharmonic interference.
The DC-DC 2 inductor current is always discontinuous,
enabling the dual outputs to be regulated independent-
ly. This allows one output to be at 100% load while the
other is at no load.
DC-DC 2 Operation
In normal operation, DC-DC 2 alternates between
charging the negative and positive outputs (Figure 1).
During the first half-cycle of the PFM clock period, both
the N-channel and P-channel MOSFETs turn on, apply-
ing the input supply across inductor L2. This causes
the inductor current to ramp up at a rate proportional to
V_INP. During the second half-cycle, the P-channel
MOSFET turns off and the inductor transfers its energy
into the negative output filter capacitor.
Assuming that the energy transfer is completed during
this second half-cycle and the inductor current ramps
down to zero, the process is repeated for the positive
output during the next clock cycle. During the first half
of the second clock cycle, both the N-channel and P-
channel MOSFETs turn on again. The current in the
inductor again rises at the same rate. During the sec-
ond half of the second clock cycle, the N-channel
MOSFET is turned off and this time the inductor energy
transfers to the positive output filter capacitor.
During conditions of heavy loads, DC-DC 2 will contin-
ue to operate in this manner, alternately delivering
pulses to the negative and positive outputs. For lighter
loads, the controller may skip one or more cycles of
either polarity, thereby keeping the outputs in regula-
tion. See Table 1 for the relationship between the maxi-
mum DC-DC 2 pulse frequency and the backplane
clock frequency.
Outputs with Low Step-Up or Inversion Ratios
For DC-DC 2 output voltage setpoints, which require
minimum step-up or inversion ratios (for example,
V_OUT+ < 6V or V_OUT- > -3V, when V_INP = 5V), more
than one half-cycle may be required to transfer the
inductor energy to the appropriate output filter capaci-
tor. In such cases, subsequent conversion cycles are
delayed, as necessary, by one or more PFM clock
cycles to preserve discontinuous mode operation.
Backplane Driver
The MAX1664 provides a low-impedance backplane dri-
ver, as shown in Figure 1, that level-translates the BPCLK
signal from a logic level to BPV_DD/BPV_SS levels. The
backplane driver consists of an N-channel/P-channel
complementary pair of high-current MOSFETs. These
devices drive BPDRV to either BPV_DD or BPV_SS when
BPCLK goes either high or low, respectively. The switch-
es have a maximum on-resistance of 0.7Ω with a typical
propagation delay of 50ns. Power for the backplane dri-
ver can be taken from the output of DC-DC 1, V_OUT1, as
shown in the Typical Operating Circuit.
Phase-Locked Loop
The MAX1664 contains an on-board PLL to synchronize
the PWM and PFM converter clocks to the backplane
clock (Figure 2). This will minimize noise and interfer-
ence. The PLL is a frequency-multiplying type, generat-
ing a nominal 1MHz clock signal for DC-DC 1 and a
nominal 500kHz clock for DC-DC 2. Three input fre-
quency ranges, spanning 20kHz to 72kHz, permit syn-
chronization over a broad range of backplane clock
input frequencies while maintaining optimal conversion
frequencies (Table 1).
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