MAX1661 Datasheet, PDF (13/16 Pages) Maxim Integrated Products – Active-Matrix Liquid Crystal Display AMLCD Supply

Active-Matrix Liquid Crystal Display
(AMLCD) Supply
Ceramic capacitors are recommended because they
have low ESR and the lowest profile. Typical ceramic
capacitors are the C3225X5R series from TDK and
JMK325 series from Taiyo Yuden. See Table 3 for more
information on the manufacturers who provide surface-
mount ceramic capacitors.
PLL Compensation
In most applications, the recommended compensation
component values shown in Figure 4 will give optimal
system performance. If no backplane clock is used,
connect PLLC to REF.
Table 3. Component Manufacturers
MANUFACTURER
PHONE
INDUCTORS
Dale Inductors
[phone]
Sumida USA
[phone]
DIODES
Central Semiconductor [phone]
International Rectifier [phone]
Motorola
[phone]
CERAMIC CAPACITORS
Marcon/United
Chemicon
[phone]
TDK
Taiyo Yuden
Vishay/Vitramon
[phone]
[phone]
[phone]
FAX
[phone]
[phone]
[phone]
[phone]
[phone]
[phone]
[phone]
[phone]
[phone]
_____________Applications Information
Increasing V_OUT Above 5.5V
For V_OUT1 output voltages above 5.5V, connect the
supplemental charge pump circuit shown in Figure 5.
The connection shown supplies a 10V 150mA output,
but other voltages from 2 x V_IN to 10V can be set by
selecting the appropriate values for R1 and R2 (see
DC-DC 1 Output section). C2–C4 are shown as parallel
combinations of 3.3µF ceramic capacitors so that a
1.1mm height restriction can be met. If height is not
restricted, then larger values can be used instead of
parallel capacitor combinations.
3.3V to -20V Charge-Pump Configuration
For applications requiring negative voltages down to
-20V, an inverting charge-pump block can be added to
the V_OUT2- output (Figure 6). Typical values for C_F and
33Ω
0.47µF
IN
INP
LX1
MAX1664
FB1
PGND1
3.3µH
V_SUPPLY
2.8V TO 3.6V
C1
3.3µF (x2)
D1 _V1
D2
C4
D3 _R1
3.3µF (x2)
91k
C2
3.3µF (x2)
10V
150mA
C3
3.3µF (x6)
50pF
R2
13k
D1, D2, D3— MBRM5817
C1, C2, C3—ALL CERAMIC TYPES
Figure 5. Charge Pump Configuration to Increase V_OUT1
Above 5.5V.
C_OUT are 0.47µF to 1µF and 4.7µF to 10µF, respective-
ly. As a general rule, C_OUT should be ten times greater
than C_F. This circuit operates as follows:
1) During the first PFM cycle, the voltage at V1 is
charged by inductor L2 to some fraction of its final
steady-state voltage, in the normal manner described
in the Detailed Description.
2) During the first half of subsequent PFM cycles, pin
LX2P is pulled to V_INP, and capacitor C_F is charged
to (V_INP +V₁ - V_D), where V_D is a diode forward
voltage.
3) During subsequent second half-cycles when LX2P
flies negatively below V1, capacitor C_F transfers
some of its energy to output capacitor C_OUT, which
then is charged to a negative voltage of approxi-
mately (V_INP + 2 x V₁ - 2x V_D).
4) This process continues until V_OUT reaches the
desired voltage, as determined by the ratio of the
FB2- feedback resistors.
5) During steady-state (in-regulation) operation, the
magnitude of the voltage at LX2P is equal to
(V_OUT / 2 - V_INP / 2 + V_D), which must be limited to
less than 10V.
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