MAX16000_12 Datasheet, PDF (9/26 Pages) Maxim Integrated Products – Low-Voltage, Quad-/Hex-/Octal-Voltage μP Supervisors

MAX16000–MAX16007
Low-Voltage, Quad-/Hex-/Octal-Voltage
µP Supervisors
Pin Description (MAX16003/MAX16004/MAX16005) (continued)
PIN
NAME
FUNCTION
16 20 2
16
TOL ^{Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance.}
Connect TOL to V_CC to select 10% threshold tolerance.
—4
6
4
Watchdog Timer Input.
MAX16004: If WDI remains low or high for longer than the watchdog timeout period,
RESET is asserted and the timer is cleared. The timer also clears whenever a reset is
asserted or a rising or falling edge on WDI is detected. The watchdog timer enters a
startup period that allows 54s for the first transition to occur before a reset. Leave WDI
unconnected to disable the watchdog timer.
WDI MAX16005: If WDI remains low or high for longer than the watchdog timeout period,
WDO is asserted. The timer clears whenever a rising or falling edge on WDI is detected.
Leave WDI unconnected to disable the watchdog timer. The MAX16005 does not have a
startup period.
MAX16004/MAX16005: The WDI open-state detector uses a small 100nA current.
Therefore, do not connect WDI to anything that will source or sink more than 50nA. Note
that the leakage current specification for most three-state drivers exceeds 50nA.
— 10 11
9
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for
MR the reset timeout period after MR is deasserted. MR is pulled up to V_CC through a 20kΩ
resistor.
— 11 12 10
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout
SRT
period. The reset timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 10⁶ (Ω) x C_SRT (F). For the internal timeout period of 140ms
(min), connect SRT to V_CC.
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls
— 16 14
12
RESET
below its respective threshold or MR is asserted. RESET remains asserted for the reset
timeout period after all monitored voltages exceed their respective thresholds and MR is
deasserted. This open-drain output has a 30µA internal pullup.
—— 9
7
— — 10
8
REF
WDO
Reference Output. The reference output voltage of 1.23V can source up to 40µA.
Active-Low Watchdog Output. WDO asserts and stays low whenever any of the IN_ inputs
fall below their respective thresholds. WDO deasserts without a timeout delay when all
the IN_ inputs rise above their thresholds. When all the IN_ inputs rise above their
thresholds, WDO asserts low whenever the watchdog timer times out. WDO deasserts
after a valid WDI transition or if MR is pulled low. The watchdog timer begins counting
after the reset timeout period once MR goes high. Pull MARGIN low to deassert WDO.
—— —
—
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to
EP provide a low thermal resistance path from the IC junction to the PCB. Do not use as the
electrical connection to GND.
Maxim Integrated
9