MAX16000_12 Datasheet, PDF (10/26 Pages) Maxim Integrated Products – Low-Voltage, Quad-/Hex-/Octal-Voltage μP Supervisors

MAX16000–MAX16007
Low-Voltage, Quad-/Hex-/Octal-Voltage
µP Supervisors
Pin Description (MAX16006/MAX16007)
PIN
NAME
FUNCTION
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
—
9
—
10
—
11
—
12
10
13
11
IN5
IN6
IN7
IN8
WDI
GND
V_CC
OUT5
OUT6
OUT7
OUT8
MR
SRT
Monitored Input Voltage 5. See Table 1 for the input voltage threshold.
Monitored Input Voltage 6. See Table 1 for the input voltage threshold.
Monitored Input Voltage 7. See Table 1 for the input voltage threshold.
Monitored Input Voltage 8. See Table 1 for the input voltage threshold.
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period,
RESET is asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a
rising or falling edge on WDI is detected. The watchdog timer enters a startup period that allows 54s
for the first transition to occur before a reset. Leave WDI unconnected to disable the watchdog timer.
The WDI open-state detector uses a small 400nA current. Therefore, do not connect WDI to anything
that will source or sink more than 200nA. Note that the leakage current specification for most three-
state drivers exceeds 200nA.
Ground
Unmonitored Power-Supply Input
Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the
voltage at IN5 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the
voltage at IN6 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
Output 7. When the voltage at IN7 falls below its threshold, OUT7 goes low and stays low until the
voltage at IN7 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
Output 8. When the voltage at IN8 falls below its threshold, OUT8 goes low and stays low until the
voltage at IN8 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset
timeout period after MR is deasserted. MR is pulled up to V_CC through a 20kΩ resistor.
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The
reset timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 10⁶ (Ω) x C_SRT (F). For the internal timeout period of 140ms (min), connect
SRT to V_CC.
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Maxim Integrated