MAX148_V5 Datasheet, PDF (9/23 Pages) Maxim Integrated Products – +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
VDD
DGND
AGND
0 TO
+2.500V
ANALOG
INPUT ^0.01µF
MAX148 ^COM
MAX149
CH7
CS
SCLK
+3V
V_OUT
MAX872
1000pF
+3V REFADJ
2.5V
C1 VREF
0.1µF
DIN
+3V
DOUT
COMP
SSTRB
OPTIONAL FOR MAX149,
REQUIRED FOR MAX148
SHDN
N.C.
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
+3V
0.1µF
2MHz
OSCILLATOR _CH1
OSCILLOSCOPE
SCLK
SSTRB
DOUT*
CH2
CH3
CH4
Figure 5. Quick-Look Circuit
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
tACQ = 7 x (RS + RIN) x 16pF
where RIN = 9kI, RS = the source impedance of the
input signal, and tACQ is never less than 1.5Fs. Note that
source impedances below 4kI do not significantly affect
the ADC’s AC performance.
Higher source impedances can be used if a 0.01FF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with
the input source impedance, limiting the ADC’s signal
bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate
by using undersampling techniques. To avoid high-
frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and AGND, allow the channel input pins to
swing from AGND - 0.3V to VDD + 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDD by more than 50mV or be
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of off
channels over 2mA.
Quick Look
To quickly evaluate the MAX148/MAX149’s analog per-
formance, use the circuit of Figure 5. The MAX148/
MAX149 require a control byte to be written to DIN
before each conversion. Tying DIN to +3V feeds in
control bytes of $FF (HEX), which trigger single-ended
unipolar conversions on CH7 in external clock mode
without powering down between conversions. In external
clock mode, the SSTRB output pulses high for one clock
period before the most significant bit of the conversion
result is shifted out of DOUT. Varying the analog input to
CH7 will alter the sequence of bits from DOUT. A total of
15 clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
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