MAX148_V5 Datasheet, PDF (7/23 Pages) Maxim Integrated Products – +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs

+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Pin Description
PIN
NAME
FUNCTION
1–8
CH0–CH7 Sampling Analog Inputs
9
COM
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5 LSB.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX148/MAX149 down; otherwise, they
10
SHDN
are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation
mode. Leaving SHDN unconnected puts the reference-buffer amplifier in external compensation
mode.
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
11
VREF
In internal reference mode (MAX149 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to VDD.
12
REFADJ Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.
13
AGND Analog Ground
14
DGND Digital Ground
15
DOUT Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX148/MAX149 begin
16
SSTRB
the A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high
(external clock mode).
17
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
18
CS
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
19
SCLK
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed (duty cycle must be 40% to 60%).
20
VDD
Positive Supply Voltage
DOUT
6kI
DGND
C_LOAD
50pF
DOUT
V_DD
6kI
C_LOAD
50pF
DGND
a) HIGH-Z TO V_OH AND V_OL TO V_OH
b) HIGH-Z TO V_OL AND V_OH TO V_OL
Figure 1. Load Circuits for Enable Time
DOUT
6kI
DGND
a) V_{OH TO} HIGH-Z
C_LOAD
50pF
DOUT
V_DD
6kI
C_LOAD
50pF
DGND
b) V_{OL TO} HIGH-Z
Figure 2. Load Circuits for Disable Time
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