MAX1245_09 Datasheet, PDF (9/21 Pages) Maxim Integrated Products – +2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
where R_IN = 12kΩ, R_S = the source impedance of the
input signal, and t_ACQ is never less than 2.0µs. Note
that source impedances below 1kΩ do not significantly
affect the AC performance of the ADC. Higher source
impedances can be used if an input capacitor is con-
nected to the analog inputs, as shown in Figure 5. Note
that the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s signal bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to V_DD and AGND, allow the channel input pins to
swing from AGND - 0.3V to V_DD + 0.3V without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed V_DD by more than 50mV or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over two milliamperes, as excessive
current will degrade the conversion accuracy of the
on channel.
Quick Look
To quickly evaluate the MAX1245’s analog perfor-
mance, use the circuit of Figure 5. The MAX1245
requires a control byte to be written to DIN before each
conversion. Tying DIN to V_DD feeds in control bytes of
$FF (HEX), which trigger single-ended unipolar conver-
sions on CH7 in external clock mode without powering
down between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the 12-bit conversion result is
shifted out of DOUT. Varying the analog input to CH7
alters the sequence of bits from DOUT. A total of 15
clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
How to Start a Conversion
A conversion is started by clocking a control byte into
DIN. With CS low, each rising edge on SCLK clocks a
bit from DIN into the MAX1245’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
MSB of the control byte. Until this first “start” bit arrives,
any number of logic “0” bits can be clocked into DIN
with no effect. Table 1 shows the control-byte format.
The MAX1245 is compatible with Microwire, SPI, and
QSPI devices. For SPI, select the correct clock polarity
and sampling edge in the SPI control registers: set
CPOL = 0 and CPHA = 0. Microwire, SPI, and QSPI all
transmit a byte and receive a byte at the same time.
Using the Typical Operating Circuit, the simplest soft-
ware interface requires only three 8-bit transfers to
0V TO
2.048V
ANALOG
INPUT 0.01μF
2.048V
C1
0.1μF
MAX1245
CH7
VREF
V_DD
DGND
AGND
COM
CS
SCLK
DIN
DOUT
SSTRB
SHDN
Figure 5. Quick-Look Circuit
+2.5V
0.1μF
OSCILLOSCOPE
SCLK
+2.5V
N.C.
1.5MHz
OSCILLATOR
SSTRB
DOUT*
CH1
CH2
CH3
CH4
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
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