MAX1245_09 Datasheet, PDF (7/21 Pages) Maxim Integrated Products – +2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
______________________________________________________________Pin Description
PIN
1–8
9
10
11
12, 20
13
14
15
16
17
18
19
NAME
CH0–CH7
COM
SHDN
VREF
V_DD
AGND
DGND
DOUT
SSTRB
DIN
CS
SCLK
Sampling Analog Inputs
FUNCTION
Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1245 down to 10µA (max) supply current;
otherwise, the MAX1245 is fully operational. Letting SHDN float sets the internal clock frequency to 1.5MHz.
Pulling SHDN high sets the internal clock frequency to 225kHz. See Hardware Power-Down section.
External Reference Voltage Input for analog-to-digital conversion
Positive Supply Voltage
Analog Ground
Digital Ground
Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1245 begins the A/D con-
version and goes high when the conversion is done. In external clock mode, SSTRB pulses high for
one clock period before the MSB decision. High impedance when CS is high (external clock mode).
Serial Data Input. Data is clocked in at the rising edge of SCLK.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
V_DD
DOUT
6k
DOUT
6k
C_LOAD
50pF
DGND
C_LOAD
50pF
DGND
a) High-Z to V_OH and V_OL to V_OH
b) High-Z to V_OL and V_OH to V_OL
DOUT
6k
DGND
V_DD
6k
DOUT
C_LOAD
50pF
C_LOAD
50pF
DGND
a) V_OH to High-Z
b) V_OL to High-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
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