MAX1245_09 Datasheet, PDF (14/21 Pages) Maxim Integrated Products – +2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
The fastest the MAX1245 can run is 15 clocks per conver-
sion with CS held low between conversions. Figure 11a
shows the serial-interface timing necessary to perform a
conversion every 15 SCLK cycles in external clock mode.
If CS is low and SCLK is continuous, guarantee a start bit
by first clocking in 16 zeros.
Most microcontrollers require that conversions occur in
multiples of eight SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can
drive the MAX1245. Figure 11b shows the serial-inter-
face timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
__________ Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1245 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies have stabi-
lized, the internal reset time is 10µs, and no conver-
sions should be performed during this phase. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
DIN will be interpreted as a start bit. Until a conversion
takes place, DOUT shifts out zeros.
Power-Down
The MAX1245’s automatic power-down mode can save
considerable power when operating at speeds below
the maximum sampling rate. Figure 13 shows the aver-
age supply current as a function of the sampling rate.
You can save power by placing the converter in a low-
current shutdown state between conversions.
Select power-down via bits 1 and 0 of the DIN control
byte with SHDN high (Tables 1 and 4). Pull SHDN low at
any time to shut down the converter completely. SHDN
overrides bits 1 and 0 of the control byte (Table 5).
Power-down mode turns off all chip functions that draw
quiescent current, reducing I_DD typically to 1.2µA.
Figures 12a and 12b illustrate the various power-down
sequences in both external and internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and PD0
of the control byte. As shown in Table 4, PD1 and PD0
CS
SCLK
DIN
DOUT
SSTRB
1
8
1
8
1
S CONTROL BYTE 0
S
CONTROL BYTE 1
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
S CONTROL BYTE 2
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 1
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
CS
SCLK
DIN
DOUT
S CONTROL BYTE 0
S CONTROL BYTE 1
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
•••
•••
•••
B11 B10 B9 B8
•••
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
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