MAX1136_09 Datasheet, PDF (9/22 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
SDA
SCL
INPUT SHIFT REGISTER
V_DD
GND
SETUP REGISTER
CONTROL
LOGIC
INTERNAL
OSCILLATOR
CONFIGURATION REGISTER
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11/REF
ANALOG
INPUT
MUX
T/H
10-BIT
ADC
REF
REFERENCE
4.096V (MAX1138)
2.048V (MAX1139)
OUTPUT SHIFT
REGISTER
AND RAM
MAX1138
MAX1139
Figure 2. MAX1138/MAX1139 Functional Diagram
V_DD
I_OL
SDA
V_OUT
400pF
I_OH
Figure 3. Load Circuit
Detailed Description
The MAX1136–MAX1139 analog-to-digital converters
(ADCs) use successive-approximation conversion tech-
niques and fully differential input track/hold (T/H) cir-
cuitry to capture and convert an analog signal to a
serial 12-bit digital output. The MAX1136/MAX1137 are
4-channel ADCs, and the MAX1138/MAX1139 are
12-channel ADCs. These devices feature a high-speed
2-wire serial interface supporting data rates up to
1.7MHz. Figure 2 shows the simplified internal structure
for the MAX1138/MAX1139.
Power Supply
The MAX1136–MAX1139 operates from a single supply
and consumes 670µA (typ) at sampling rates up to
94.4ksps. The MAX1137/MAX1139 feature a 2.048V
internal reference and the MAX1136/MAX1138 feature
a 4.096V internal reference. All devices can be config-
ured for use with an external reference from 1V to V_DD.
Analog Input and Track/Hold
The MAX1136–MAX1139 analog-input architecture con-
tains an analog-input multiplexer (mux), a fully differen-
tial track-and-hold (T/H) capacitor, T/H switches, a
comparator, and a fully differential switched capacitive
digital-to-analog converter (DAC) (Figure 4).
In single-ended mode the analog-input multiplexer con-
nects C_T/H between the analog input selected by
CS[3:0] (see the Configuration Setup Bytes section)
and GND (Table 3). In differential mode, the analog-
input multiplexer connects C_T/H to the “+” and “-” ana-
log inputs selected by CS[3:0] (Table 4).
During the acquisition interval the T/H switches are in
the track position and C_T/H charges to the analog input
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