MAX1136_09 Datasheet, PDF (5/22 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
TIMING CHARACTERISTICS (Figure 1) (continued)
(V_DD = 2.7V to 3.6V (MAX1137/MAX1139), V_DD = 4.5V to 5.5V (MAX1136/MAX1138), V_REF = 2.048V (MAX1137/MAX1139), V_REF =
4.096V (MAX1136/MAX1138), f_SCL = 1.7MHz, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C. See
Tables 1–5 for programming notation.).)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Rise Time of SCL Signal
(Current Source Enabled)
t_RCL Measured from 0.3V_DD to 0.7V_DD
20
80
ns
Rise Time of SCL Signal after
Acknowledge Bit
t_RCL1 Measured from 0.3V_DD to 0.7V_DD
20
160
ns
Fall Time of SCL Signal
t_FCL Measured from 0.3V_DD to 0.7V_DD
20
Rise Time of SDA Signal
t_RDA Measured from 0.3V_DD to 0.7V_DD
20
Fall Time of SDA Signal
t_FDA Measured from 0.3V_DD to 0.7V_DD (Note 11)
20
Setup Time for STOP (P) Condition t_SU, _STO
160
Capacitive Load for Each Bus Line C_B
Pulse Width of Spike Suppressed
t_SP
(Notes 10 and 13)
0
80
ns
160
ns
160
ns
ns
400
pF
10
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
For DC accuracy, the MAX1136/MAX1138 are tested at V_DD = 5V and the MAX1137/MAX1139 are tested at V_DD = 3V. All
devices are configured for unipolar, single-ended inputs.
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Offset nulled.
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V_DD.
When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit).
ADC performance is limited by the converter’s noise floor, typically 300µV_P-P.
Note 9: Measured as for the MAX1137/MAX1139
[ ] ^⎡
⎢
⎣
V_FS(3.6V) − V_FS(2.7V)
×
2^N −1^⎤
V_REF
⎥
⎦
(3.6V − 2.7V)
and for the MAX1136/MAX1138
[ ] ^⎡
⎢
⎣
V_FS(5.5V) − V_FS(4.5V)
×
2^N −1^⎤
V_REF
⎥
⎦
(5.5V − 4.5V)
Note 10: A master device must provide a data hold time for SDA (referred to V_IL of SCL) in order to bridge the undefined region of
SCL’s falling edge (see Figure 1).
Note 11: The minimum value is specified at +25°C.
Note 12: C_B = total capacitance of one bus line in pF.
Note 13: f_SCL must meet the minimum clock low time plus the rise/fall times.
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