MAX1136_09 Datasheet, PDF (15/22 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
CS3¹ CS2¹ CS1 CS0 AIN0 AIN1 AIN2 AIN3² AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11²
0
0
0
0
+
-
0
0
0
1
-
+
0
0
1
0
+
-
0
0
1
1
-
+
0
1
0
0
+
-
0
1
0
1
0
1
1
0
-
+
+
-
0
1
1
1
-
+
1
0
0
0
+
-
1
0
0
1
-
+
1
0
1
0
+
-
1
0
1
1
-
+
1
1
0
0
RESERVED
1
1
0
1
1
1
1
0
RESERVED
RESERVED
1
1
1
1
RESERVED
1. For MAX1136/MAX1137, CS3 and CS2 are internally set to 0.
2. When SEL1 = 1, a differential read between AIN2 and AIN3/REF (MAX1136/MAX1137) or AIN10 and AIN11/REF
(MAX1138/MAX1139) will return the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of
1011 will return the negative difference between AIN10 and GND. In differential scanning, the address increments by 2 until limit set
by CS3:CS1 has been reached.
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing
a START condition followed by seven address bits and
a read bit (R/W = 1). If the address byte is successfully
received, the MAX1136–MAX1139 (slave) issues an
acknowledge. The master then reads from the slave.
The result is transmitted in two bytes; first six bits of the
first byte are high, then MSB through LSB are consecu-
tively clocked out. After the master has received the
byte(s) it can issue an acknowledge if it wants to con-
tinue reading or a not-acknowledge if it no longer wish-
es to read. If the MAX1136–MAX1139 receive a not-
acknowledge, they release SDA allowing the master to
generate a STOP or a repeated START condition. See
the Clock Mode and Scan Mode sections for detailed
information on how data is obtained and converted.
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the set-
up byte’s CLK bit determines the clock mode (Table 1).
At power-up the MAX1136–MAX1139 are defaulted to
internal clock mode (CLK = 0).
Internal Clock
When configured for internal clock mode (CLK = 0), the
MAX1136–MAX1139 use their internal oscillator as the con-
version clock. In internal clock mode, the MAX1136–
MAX1139 begin tracking the analog input after a valid
address on the eighth rising edge of the clock. On the
falling edge of the ninth clock the analog signal is acquired
and the conversion begins. While converting the analog
input signal, the MAX1136–MAX1139 holds SCL low (clock
stretching). After the conversion completes, the results are
stored in internal memory. If the scan mode is set for multi-
ple conversions, they will all happen in succession
with each additional result stored in memory.The
MAX1136/MAX1137 contain four 10-bit blocks of memory,
and the MAX1138/MAX1139 contain twelve 10-bit blocks
of memory. Once all conversions are complete, the
MAX1136–MAX1139 release SCL allowing it to be pulled
high. The master may now clock the results out of the
memory in the same order the scan conversion has been
done at a clock rate of up to 1.7MHz. SCL will be stretched
for a maximum of 7.6µs per channel (see Figure 10).
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