 English |
|
|
|
|
|
|
|
| MAX1115 Datasheet, PDF (9/12 Pages) Maxim Integrated Products – Single-Supply, Low-Power, Serial 8-Bit ADCs | |||
| |||
| ◁ |
Single-Supply, Low-Power, Serial 8-Bit ADCs
ACTIVE
tCSH
CH0
CNVST
VDD
2
tCONV
POWER-DOWN MODE
tch
tcp
tCSL
CH0
VDD
2
tccs
SCLK
IDLE LOW
tcsd
DOUT
tcd
tcl
IDLE LOW
tchz
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
Figure 6c. Conversion and Interface Timing, Conversion on VDD / 2 with SCLK Idle Low
ACTIVE
tCSH
CH0
CNVST
VDD
2
tCONV
SCLK
IDLE HIGH
POWER-DOWN MODE
tch
tcp
tcsl
VDD
CH0
2
tccs
IDLE HIGH
tcsd
DOUT
tcd
tcl
tchz
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
Figure 6d. Conversion and Interface Timing, Conversion on VDD / 2 with SCLK Idle High
After CNVST is brought low, allow 7.5µs for the conver-
sion to be completed. While the internal conversion is in
progress, DOUT is low. The MSB is present at the
DOUT pin immediately after conversion is completed.
The conversion result is clocked out at the DOUT pin
and is coded in straight binary (Figure 7). Data is
clocked out at SCLKâs falling edge in MSB-first format
at rates up to 5MHz. Once all data bits are clocked out,
DOUT goes high impedance (100ns to 500ns after the
rising edge) of the eighth SCLK pulse.
SCLK is ignored during the conversion process. Only
after a conversion is complete will SCLK cause serial
data to be output. Falling edges on CNVST during an
_______________________________________________________________________________________ 9
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese