MAX1115 Datasheet, PDF (8/12 Pages) Maxim Integrated Products – Single-Supply, Low-Power, Serial 8-Bit ADCs

Single-Supply, Low-Power, Serial 8-Bit ADCs
ACTIVE
t_CSH
POWER-DOWN MODE
CNVST
CH0
t_CONV
t_ch
t_cp
CH0
t_ccs
SCLK IDLE LOW
t_csd
DOUT
t_cd
t_cl
IDLE LOW
t_chz
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
Figure 6a. Conversion and Interface Timing, Conversion on CH0 with SCLK Idle Low
ACTIVE
t_CSH
POWER-DOWN MODE
CNVST
CH0
t_CONV
t_ch
t_cp
SCLK IDLE HIGH
CH0
t_ccs
IDLE HIGH
t_csd
DOUT
t_cd
t_cl
t_chz
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0
Figure 6b. Conversion and Interface Timing, Conversion on CH0 with SCLK Idle High
Digital Inputs and Outputs
The MAX1115/MAX1116 perform conversions by using
an internal clock. This frees the µP from the burden of
running the SAR conversion clock, and allows the con-
version results to be read back at the µP’s convenience
at any clock rate up to 5MHz.
The acquisition interval begins with the falling edge of
CNVST. CNVST can idle between conversions in either
a high or low state. If idled in a low state, CNVST must
be brought high for at least 50ns, then brought low to
initiate a conversion. To select V_DD/2 for conversion,
the CNVST pin must be brought high and low for a
second time (Figures 6c and 6d).
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