MAX1115 Datasheet, PDF (6/12 Pages) Maxim Integrated Products – Single-Supply, Low-Power, Serial 8-Bit ADCs

Single-Supply, Low-Power, Serial 8-Bit ADCs
Pin Description
PIN
NAME
FUNCTION
1
V_DD
Positive Supply Voltage
2
CH0
Analog Voltage Input
3, 5
I.C.
Internally Connected. Connect to ground.
4
GND
Ground
6
CNVST Convert/Start Input. CNVST initiates a power-up and starts a conversion on its falling edge.
Serial Data Output. Data is clocked out on the falling edge of SCLK. DOUT goes low at the start of a
7
DOUT
conversion and presents the MSB at the completion of a conversion. DOUT goes high impedance
once data has been fully clocked out.
8
SCLK
Serial Clock. Used for clocking out data on DOUT.
V_DD
V_DD
DOUT
3kΩ
DOUT
DOUT
3kΩ
DOUT
3kΩ
GND
a) V_OL TO V_OH
C_LOAD
C_LOAD
GND
b) HIGH-Z TO V_OL AND V_OH TO V_OL
Figure 1. Load Circuits for Enable Time
3kΩ
GND
C_LOAD
C_LOAD
GND
a) V_OH TO HIGH-Z
b) V_OL TO HIGH-Z
Figure 2. Load Circuits for Disable Time
Detailed Description
The MAX1115/MAX1116 ADCs use a successive-
approximation conversion technique and input
track/hold (T/H) circuitry to convert an analog signal to
an 8-bit digital output. The SPI/QSPI/MICROWIRE-
compatible interface directly connects to microproces-
sors (µPs) without additional circuitry (Figure 3).
Track/Hold
The input architecture of the ADC is illustrated in the
equivalent-input circuit shown in Figure 4 and is com-
posed of the T/H, input multiplexer, input comparator,
switched capacitor DAC, and auto-zero rail.
The acquisition interval begins with the falling edge of
CNVST. During the acquisition interval, the analog input
(CH0) is connected to the hold capacitor (C_HOLD).
Once the acquisition is complete, the T/H switch opens
and C_HOLD is connected to GND, which retains the
charge on C_HOLD as a sample of the signal at the ana-
log input.
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance of <1.5kΩ is
recommended for accurate sample settling. A 100pF
capacitor at the ADC inputs also improves the accuracy
of an input sample.
Conversion Process
The MAX1115/MAX1116 conversion process is internal-
ly timed. The total acquisition and conversion process
takes <7.5µs. Once an input sample has been
acquired, the comparator’s negative input is then con-
nected to an auto-zero supply. Since the device
requires only a single supply, the negative input of the
comparator is set to equal V_DD/2. The capacitive DAC
restores the positive input to V_DD/2 within the limits of 8-
bit resolution. This action is equivalent to transferring a
charge Q_IN = 16pF ✕ V_IN from C_HOLD to the binary-
weighted capacitive DAC, which forms a digital repre-
sentation of the analog-input signal.
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