MAX11102 Datasheet, PDF (9/25 Pages) Maxim Integrated Products – 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs

2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11111/MAX11115/MAX11116) (continued)
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps (MAX11111/MAX11116); fSCLK = 32MHz,
50% duty cycle, 2Msps (MAX11115), CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA =
+25NC.)
PARAMETER
CS Falling Until DOUT High
Impedance Disabled
SYMBOL
t3
(Note 1)
CONDITIONS
Data Access Time After SCLK
Y _{Falling Edge}
t4
Figure 2
VOVDD = 2.2V - 3.6V
VOVDD = 1.5V - 2.2V
SCLK Pulse Width Low
t5
Percentage of clock period
SCLK Pulse Width High
t6
Percentage of clock period
R Data Hold Time from SCLK Falling
Edge
t7
Figure 3
SCLK Falling Until DOUT High
Impedance
t8
Figure 4 (Note 1)
A _{Power-Up Time}
Conversion cycle
Note 1: Guaranteed by design and characterization; not production tested.
Note 2: VOVDD is tied to VDD internally for all SOT devices.
PRELIMIN ^{Note 3: All timing specifications given are with a 10pF load capacitor.}
MIN TYP MAX UNITS
1
ns
15
ns
16.5
40
60
%
40
60
%
5
ns
2.5
14
ns
1 Cycles
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