MAX11102 Datasheet, PDF (21/25 Pages) Maxim Integrated Products – 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs

2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
Dual-Channel Operation
Applications Information
The MAX11102/MAX11103/MAX11106/MAX11111 fea-
Layout, Grounding, and Bypassing
ture dual-input channels. These devices use a channel-
For best performance, use PCBs with a solid ground
select (CHSEL) input to select between analog input AIN1
(CHSEL = 0) or AIN2 (CHSEL = 1). As shown in Figure
15, the CHSEL signal is required to change between the
2nd and 12th clock cycle within a regular conversion to
guarantee proper switching between channels.
Y _{14-Cycle Conversion Mode}
The ICs can operate with 14 cycles per conversion.
Figure 16 shows the corresponding timing diagram.
R ^{Observe that DOUT does not go into high-impedance}
mode. Also, observe that tACQ needs to be sufficiently
long to guarantee proper settling of the analog input
voltage. See the Electrical Characteristics table for tACQ
A requirements and the Analog Input section for a descrip-
tion of the analog inputs.
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the ADC package. Noise in the VDD
power supply, OVDD, and REF affects the ADC’s perfor-
mance. Bypass the VDD, OVDD, and REF to ground with
0.1FF and 10FF bypass capacitors. Minimize capacitor
lead and trace lengths for best supply-noise rejection.
Choosing an Input Amplifier
It is important to match the settling time of the input
amplifier to the acquisition time of the ADC. The conver-
sion results are accurate when the ADC samples the
input signal for an interval longer than the input signal’s
worst-case settling time. By definition, settling time is
the interval between the application of an input voltage
step and the point at which the output signal reaches
IN _CS
SCLK
IM ^CHSEL
DOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DATA CHANNEL AIN2
L _{Figure 15. Channel Select Timing Diagram}
SAMPLE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DATA CHANNEL AIN1
SAMPLE
E _CS
PR ^SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
DOUT
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
(MSB)
tACQ
1/fSAMPLE
tCONVERT
Figure 16. 14-Clock Cycle Operation
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