MAX11102 Datasheet, PDF (6/25 Pages) Maxim Integrated Products – 2Msps/3Msps, Low-Power, Serial 12-/10-/8-Bit ADCs

2Msps/3Msps, Low-Power,
Serial 12-/10-/8-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX11106/MAX11110/MAX11117) (continued)
(VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD, fSCLK = 48MHz, 50% duty cycle, 3Msps (MAX11106/MAX11117); fSCLK = 32MHz,
50% duty cycle, 2Msps (MAX11110), CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA =
+25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Reference Input Capacitance
CREF
DIGITAL INPUTS (SCLK, CS, CHSEL)
Digital Input High Voltage
VIH
(Note 2)
75
Y _{Digital Input Low Voltage}
VIL
(Note 2)
Digital Input Hysteresis
VHYST (Note 2)
Digital Input Leakage Current
IIL
Inputs at GND or VDD
R ^{Digital Input Capacitance}
CIN
DIGITAL OUTPUT (DOUT)
Output High Voltage
VOH
ISOURCE = 200µA (Note 2)
85
Output Low Voltage
VOL
ISINK = 200µA (Note 2)
A _{High-Impedance Leakage}
Current
IOL
High-Impedance Output
IN ^Capacitance
COUT
POWER SUPPLY
Positive Supply Voltage
Digital I/O Supply Voltage
Positive Supply Current (Full-
IM ^{Power Mode)}
Positive Supply Current (Full-
Power Mode), No Clock
VDD
2.2
VOVDD MAX11106
1.5
fSAMPLE = 3Msps, MAX11106, VIN = GND
IVDD fSAMPLE = 2Msps, MAX11110, VIN = GND
fSAMPLE = 3Msps, MAX11117, VIN = GND
IOVDD MAX11106
IVDD
MAX11106/MAX11117
MAX11110
L _{Power-Down Current}
IPD
Line Rejection
TIMING CHARACTERISTICS (Note 3)
Leakage only
VDD = 2.2V to 3.6V, VREF = 2.2V
E _{Quiet Time}
tQ
4
CS Pulse Width
t1
10
CS Fall to SCLK Setup
t2
5
R ^{CS Falling Until DOUT High}
Impedance Disabled
t3
(Note 1)
1
Data Access Time After SCLK
P ^{Falling Edge}
t4
Figure 2
VOVDD = 2.2V - 3.6V
VOVDD = 1.5V - 2.2V
TYP MAX UNITS
5
pF
15
0.001
2
%OVDD
25 %OVDD
%OVDD
Q1
FA
pF
15
Q1.0
%OVDD
%OVDD
FA
4
pF
3.6
V
VDD
V
3.3
2.6
mA
3.55
0.33
1.98
mA
1.48
1.3
10
FA
0.17
LSB/V
ns
ns
ns
ns
15
ns
16.5
SCLK Pulse Width Low
t5
Percentage of clock period
40
60
%
SCLK Pulse Width High
t6
Percentage of clock period
40
60
%
Data Hold Time from SCLK
Falling Edge
t7
Figure 3
5
ns
SCLK Falling Until DOUT High
Impedance
t8
Figure 4 (Note 1)
2.5
14
ns
Power-Up Time
Conversion cycle
1
Cycle
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