MAX1072 Datasheet, PDF (9/18 Pages) Maxim Integrated Products – 1.8Msps, Single-Supply, Low-Power, True-Differential, 10-Bit ADCs

1.8Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
REF
AIN +
T/H
AIN -
V_DD
V_L
10-BIT
SAR
ADC
OUTPUT
BUFFER
MAX1072
MAX1075
CONTROL
LOGIC AND
TIMING
RGND
GND
Figure 3. Functional Diagram
DOUT
CNVST
SCLK
C_{IN+ RIN+}
AIN+
V_AZ
COMP
AIN-
C_IN- ^RIN-
ACQUISITION MODE
C_{IN+ RIN+}
AIN+
V_AZ
COMP
AIN-
C_IN-
R_IN-
HOLD/CONVERSION MODE
Figure 4. Equivalent Input Circuit
CAPACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
CONTROL
LOGIC
Serial Interface
Initialization After Power-Up
and Starting a Conversion
Upon initial power-up, the MAX1072/MAX1075 require a
complete conversion cycle to initialize the internal cali-
bration. Following this initial conversion, the part is ready
for normal operation. This initialization is only required
after a hardware power-up sequence and is not required
after exiting partial or full power-down mode.
To start a conversion, pull CNVST low. At CNVST’s
falling edge, the T/H enters its hold mode and a con-
version is initiated. SCLK runs the conversion and the
data can then be shifted out serially on DOUT.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CNVST and SCLK digital inputs. Figures
1 and 5 show timing diagrams, which outline the serial-
interface operation.
A CNVST falling edge initiates a conversion sequence;
the T/H stage holds the input voltage, the ADC begins
to convert, and DOUT changes from high impedance
to logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of the con-
version is determined.
SCLK begins shifting out the data after the 4th rising
edge of SCLK. DOUT transitions t_DOUT after each
SCLK’s rising edge and remains valid 4ns (t_DHOLD)
after the next rising edge. The 4th rising clock edge
produces the MSB of the conversion at DOUT, and the
MSB remains valid 4ns after the 5th rising edge. Since
there are 10 data bits, 2 sub-bits (S1 and S0), and 3
leading zeros, at least 16 rising clock edges are need-
ed to shift out these bits. For continuous operation, pull
CNVST high between the 14th and the 16th SCLK ris-
ing edges. If CNVST stays low after the falling edge of
the 16th SCLK cycle, the DOUT line goes to a high-
impedance state on either CNVST’s rising edge or the
next SCLK’s rising edge.
Partial Power-Down and
Full Power-Down Modes
Power consumption can be reduced significantly by
placing the MAX1072/MAX1075 in either partial power-
down mode or full power-down mode. Partial power-
down mode is ideal for infrequent data sampling and
fast wake-up time applications. Pull CNVST high after
the 3rd SCLK rising edge and before the 14th SCLK
rising edge to enter and stay in partial power-down
mode (see Figure 6). This reduces the supply current
to 1mA. Drive CNVST low and allow at least 14 SCLK
cycles to elapse before driving CNVST high to exit par-
tial power-down mode.
Full power-down mode is ideal for infrequent data sam-
pling and very low supply current applications. The
MAX1072/MAX1075 have to be in partial power-down
mode in order to enter full power-down mode. Perform the
SCLK/CNVST sequence described above to enter partial
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