MAX1072 Datasheet, PDF (11/18 Pages) Maxim Integrated Products – 1.8Msps, Single-Supply, Low-Power, True-Differential, 10-Bit ADCs

1.8Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
Applications Information
External Reference
An external reference is required for the MAX1072/
MAX1075. Use a 4.7µF and 0.01µF bypass capacitor on
the REF pin for best performance. The reference input
structure allows a voltage range of +1V to V_DD.
How to Start a Conversion
An analog-to-digital conversion is initiated by CNVST,
clocked by SCLK, and the resulting data is clocked out
on DOUT by SCLK. With SCLK idling high or low, a
falling edge on CNVST begins a conversion. This causes
the analog input stage to transition from track to hold
mode, and DOUT to transition from high impedance to
being actively driven low. A total of 16 SCLK cycles are
required to complete a normal conversion. If CNVST is
low during the 16th falling SCLK edge, DOUT returns to
high impedance on the next rising edge of CNVST or
SCLK, enabling the serial interface to be shared by multi-
ple devices. If CNVST returns high after the 14th, but
before the 16th SCLK rising edge, DOUT remains active
so continuous conversions can be sustained. The high-
est throughput is achieved when performing continuous
conversions. Figure 10 illustrates a conversion using a
typical serial interface.
Connection to
Standard Interfaces
The MAX1072/MAX1075 serial interface is fully compati-
ble with SPI/QSPI and MICROWIRE (see Figure 11). If a
serial interface is available, set the CPU’s serial interface
in master mode so the CPU generates the serial clock.
Choose a clock frequency up to 28.8MHz.
SPI and MICROWIRE
When using SPI or MICROWIRE, the MAX1072/MAX1075
are compatible with all four modes programmed with the
CPHA and CPOL bits in the SPI or MICROWIRE control
register. Conversion begins with a CNVST falling edge.
DOUT goes low, indicating a conversion is in progress.
Two consecutive 1-byte reads are required to get the full
10 bits from the ADC. DOUT transitions on SCLK rising
edges. DOUT is guaranteed to be valid t_DOUT later and
remains valid until t_DHOLD after the following SCLK rising
edge. When using CPOL = 0 and CPHA = 0 or CPOL = 1
and CPHA = 1, the data is clocked into the µP on the
following rising edge. When using CPOL = 0 and CPHA
= 1 or CPOL = 1 and CPHA = 0, the data is clocked
into the µP on the next falling edge. See Figure 11 for
connections and Figures 12 and 13 for timing. See the
Timing Characteristics section to determine the best
mode to use.
OUTPUT CODE
111...111
111...110
111...101
FULL-SCALE
TRANSITION
000...011
000...010
000...001
000...000
012 3
FS = V_REF
ZS = 0
1 LSB = ^VREF
1024
DIFFERENTIAL INPUT
VOLTAGE (LSB)
FS
FS - 3/2 LSB
Figure 8. Unipolar Transfer Function (MAX1072 Only)
OUTPUT CODE
011...111
011...110
000...010
000...001
000...000
111...111
111...110
111...101
FS = ^VREF
2
ZS = 0
- FS = ^-VREF
2
1 LSB = ^VREF
1024
FULL-SCALE
TRANSITION
100...001
100...000
FS
0
FS
DIFFERENTIAL INPUT
FS - 3/2 LSB
VOLTAGE (LSB)
Figure 9. Bipolar Transfer Function (MAX1075 Only)
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